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Trying to make understanding code easier with small refactoring and renaming.
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We do flush for cmd buffer in case there isn't enough space left for whole
rendering operation. This protects dma regions from getting released in middle
of state emit.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Calling EnsureCmdBufSpace is not required because rendering pipeline has to quarentee free space.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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This patch makes render emit size prediction count the corect maximum emit size
for state.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Patch adds prediction functionthat tries to predict emit size to the smallest
possible values that is quarenteed to be higher than worst case scenario in
rendering pipeline.
State emit size prediction code is in place but fix for emit sizes is included
in next patch.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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NOTE: THIS REQUIRES AN UPDATED DRM!
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(corresponding fix to the intel driver one)
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Reported to fix corruption while dragging an active window by John Bridgman.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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This alleviates the need for an additional symbol.
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This allows double buffered apps to run, but perfomance
will be awful until we implement something faster.
You must update to the latest kernel modules.
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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This function takes a GLint not a GLuint, passing in -1
breaks internally.
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Port fixes to read buffer from front.
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The _Enabled field isn't updated at the point that DrawBuffers is called,
and the Driver.Enable() function does the testing for stencil buffer
presence anyway.
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This updates some of the clear code from Intel gives a 5x clearspd perf
for me here. played openarena also, not sure if the viewport changes
broke anything,
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fgl_glxgears -fbo runs, though the gears don't look right yet.
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This moves a big chunk of the space checking code into libdrm so
it can be shared by the DDX.
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if its on the list its on the list don't go readding it.
multitexturing from the same texture could cause this.
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We flush the command buffer so we don't emit mixed
state (with new and previous buffer size) command
buffer, this is especialy affecting zbuffer states.
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To avoid locking bug we shouldn't not call firevertices from this path
as it's call from radeon get lock.
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The duplication of state data caused a crash due to double-free on destruction
of context, because a variable wasn't correctly null'ed out.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Fixes
glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion
`oldRb->Magic == 0xaabbccdd' failed.
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ctx->Stencil._Enabled is derived state and not immediately updated
when the stencil parameters are changed; we need to make sure that
it is up-to-date before accessing it.
https://bugs.freedesktop.org/show_bug.cgi?id=21608
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In radeon_clear_tris(), when clearing the stencil buffer,
pass GL_FRONT_AND_BACK to _mesa_StencilFuncSeparate(), to avoid
triggering a software fallback on r300 and below.
https://bugs.freedesktop.org/show_bug.cgi?id=21601
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this make gnome shell run
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This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.
This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
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Re work depth issues.
Do a lot more FBO abstactions
fixup depth/stencil buffer interactions
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Conflicts:
src/mesa/drivers/dri/r300/r300_cmdbuf.c
src/mesa/drivers/dri/r300/r300_state.c
src/mesa/drivers/dri/r300/r300_swtcl.c
src/mesa/drivers/dri/r300/radeon_ioctl.c
src/mesa/drivers/dri/radeon/radeon_screen.c
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radeonScheduleSwap() already takes the lock in the SwapBuffers case, only
the CopySubBuffer case was missing it.
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Otherwise they fail with AIGLX at least.
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