Age | Commit message (Collapse) | Author |
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Just add the gl_api parameter to _mesa_create_context().
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Hopefully better than previous - this passes more mipgen tests
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Default group bytes to 512 on evergreen. Don't query
tiling config yet for evergreen, the current info returned is not
adequate for evergreen (no way to get bank info).
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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=31617
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=31400
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By calling radeon_draw_buffers (which sets the necessary flags
in radeon->NewGLState) and revalidating if NewGLState is non-zero
in r200TclPrimitive. This fixes an assert in libdrm (the color-/
depthbuffer was changed but not yet validated) and and stops the
kernel cs checker from complaining about them (when they're too
small).
Thanks to Mario Kleiner for the hint to call radeon_draw_buffer
(instead of my half-broken hack).
v2: Also fix the swtcl r200 path.
Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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taken from Dave's r600g fix
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Otherwise, when we switch to an indirect glx context and then back, it looks
like we're still current.
https://bugs.freedesktop.org/show_bug.cgi?id=29977#c7
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
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Requires tiling config ioctl support from the drm to use.
kms only.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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When a DRI2 swap buffer is pending we need to make sure we
have the flush extension so radeon doesn't resume rendering to
or reading from the not yet blitted front buffer.
This fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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This reverts commit 8446f257b3e3ca4a3eb2c79bc357e46343e04e87.
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When DRI2 swap buffer is pending (copy buffer not pageflipping)
we need to make sure we have the flush extension so radeon doesn't
resume rendering on the not yet blitted front buffer.
Modified version of Jerome's patch to add flush extension
in the correct place.
This prepares a possible fix for:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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This avoids calling radeonFlush() during context destruction, when
ctx->DrawBuffer would be NULL.
NOTE: This is a candidate for the 7.8 branch.
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As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
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Tested on r300 only, other cards may require adjusting texture_compressed_row_align.
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_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This reverts commit 651cffd626a82d9bf539437ca4bdf8ea4b396fab.
The commit inadvertantly introduced a new gallium dependency on the meta code.
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I inherited this and really it stayed around far too long,
make it nice and simple.
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Converted r100 to use shared debug code with sed and fast compile check. New
code has compability layer so old debugging code doesn't have to be changed
all immidiatly.
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switches more state handling to common code. We need
should be more fine grained with the state atoms
eventually.
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We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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Reference counting protects DRM lock call from recursive locking that would
cause hang. Code also adds optional debugging output for recursive call that
is compiled only if NDEBUG is not defined.
This code is not 100% thread safe because mesa doesn't include increment and
test atomic operation. There is built-in gcc functions but they are only
available from gcc 4.2.
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Only really got good testing on r500 so far, need to enable in
DDX and play some more.
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This almost fixes compressed mipmapped textures on r200, though some small
mip levels are still broken.
Leave r300 compressed texture stride as is though afaik it's different
to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride
at same place.
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fixes texwrap
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This fixes problem that glxinfo was reporting r600+ cards as unknown.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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patch from Kevin DeKorte with some minor fixes from me.
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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Port fixes to read buffer from front.
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half stealing the code without taking the intel regions
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