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Requires tiling config ioctl support from the drm to use.
kms only.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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When a DRI2 swap buffer is pending we need to make sure we
have the flush extension so radeon doesn't resume rendering to
or reading from the not yet blitted front buffer.
This fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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This reverts commit 8446f257b3e3ca4a3eb2c79bc357e46343e04e87.
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When DRI2 swap buffer is pending (copy buffer not pageflipping)
we need to make sure we have the flush extension so radeon doesn't
resume rendering on the not yet blitted front buffer.
Modified version of Jerome's patch to add flush extension
in the correct place.
This prepares a possible fix for:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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Check if the native blit formats are supported, if not,
attempt to use an alternate format.
Skip 3, >4 bpp as per comments from mcencora on irc.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
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This moves the bo mapping outside the DMA layer and makes it explicit,
this should in theory make it simpler to split the clean up the dma/cmdbuf
linkage that I created before that is broken.
Tested on: r600, rv380 (tcl/no-tcl), rv200 (tcl/no-tcl)
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Indetion can be used to make it easier to read debug code when sections of debug output are indented.
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Converted r100 to use shared debug code with sed and fast compile check. New
code has compability layer so old debugging code doesn't have to be changed
all immidiatly.
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DRI1 didn't have support for command buffer emit for stripple.
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Swtcl calls flush everytime primitive changes so prediction has to made again
after flushing.
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We were check command buffer sizes too alte so allocated dma regions
were freed before relocations so space checking failed.
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Scissors are jsut one of states that we have to emit so it should be in state list
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This fixes problems when application is using large vertex arrays for drawing.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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Reference counting protects DRM lock call from recursive locking that would
cause hang. Code also adds optional debugging output for recursive call that
is compiled only if NDEBUG is not defined.
This code is not 100% thread safe because mesa doesn't include increment and
test atomic operation. There is built-in gcc functions but they are only
available from gcc 4.2.
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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fixes texwrap
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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Port fixes to read buffer from front.
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This updates some of the clear code from Intel gives a 5x clearspd perf
for me here. played openarena also, not sure if the viewport changes
broke anything,
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texture bo setup isn't quite working yet
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half stealing the code without taking the intel regions
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The duplication of state data caused a crash due to double-free on destruction
of context, because a variable wasn't correctly null'ed out.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Fixes
glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion
`oldRb->Magic == 0xaabbccdd' failed.
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Looks like r400 based IGP chips require 64 byte alignment
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This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.
This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
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Context destruction was nearly the same over all the drivers,
so collapse it down.
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Re work depth issues.
Do a lot more FBO abstactions
fixup depth/stencil buffer interactions
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