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seems it got lost in commit 0d383547
have no earlier radeons to test, but npot mipmaps were not supported there?
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When searching for valid miptree check images in range
of [BaseLeve, MaxLevel] not [MinLod, MaxLoad].
Prevents unnecessary miptree allocations in cases when during
every rendering operation different texture image level
was selected using MIN_LOD = MAX_LOD = level (for every level
new miptree for whole texture was allocated).
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Always store selected miptree in texObj->mt so get_base_teximage_offset returns correct data.
Found with piglit/mipmap-setup.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Declaring the loop index inside for () is not supported by this version.
Signed-off-by: Brian Paul <brianp@vmware.com>
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supported by hw
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Changed stride size calculation to do the math by rounding
the value instead of loop. r600 minimum stride is 256 which
might might cause up to about 60 rounds of the loop.
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Conflicts:
src/mesa/main/version.h
src/mesa/state_tracker/st_atom_shader.c
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Conflicts:
src/mesa/drivers/dri/r600/r700_assembler.c
src/mesa/main/version.h
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memcpy would give incorrect results if src rowstride != dst rowstride
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Fixes #21501
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Conflicts:
src/gallium/drivers/svga/svga_screen_texture.c
src/gallium/state_trackers/xorg/xorg_composite.c
src/gallium/state_trackers/xorg/xorg_exa.c
src/gallium/state_trackers/xorg/xorg_renderer.c
src/gallium/state_trackers/xorg/xorg_xv.c
src/mesa/main/texgetimage.c
src/mesa/main/version.h
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Simplify gl image level <-> miptree level mapping (are equal now).
Don't allocate miptree for images that won't fit in it (fixes #25230).
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miptrees
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This makes the miptree rounds up to the near POT for each level for
all radeons, however since mipmaps aren't support with NPOT on previous
radeons this calculation shouldn't cause any problems. If it does
we can just make it r600 only.
I tested a few mipmap demos on r500 and they all seem to work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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- typo
- memory leak
- off by one (spotted by airlied)
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Tested on r300 only, other cards may require adjusting texture_compressed_row_align.
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Use _mesa_format_image_size() instead.
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And remove other unneeded #includes while we're at it.
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Use _mesa_is_format_compressed() instead.
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Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
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We need to figure out if the compression format changes.
without this texcmp segfaults if you change format
enough times.
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Converted r100 to use shared debug code with sed and fast compile check. New
code has compability layer so old debugging code doesn't have to be changed
all immidiatly.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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another case of image never matching miptree in case of compressed textures
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- fix not respecting required hardware stride with compressedTexImage -
this fixes #22615.
- make sure correct stride is used in various places
- fix stored miptree never matching with a TexImage call with compressed
texture
- don't always store data with compressedtexsubimage at offset 0,
and actually use the supplied pixel data... (untested)
- make sure rows for compressed texture handling are rounded up not down
Note that trying to access stored compressed textures in hardware miptrees
from core mesa (get_compressed_teximage, swrast fallbacks) can't work correctly,
since RowStride isn't really set to anything useful, plus some places (at least
get_compressed_teximage) assume this data has native stride and no padding.
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fixes texwrap
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This is just a workaroung until we properly fix texture mapping in radeonSpanRenderStart
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