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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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Conflicts:
src/mesa/drivers/dri/r300/r300_draw.c
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Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Reference counting protects DRM lock call from recursive locking that would
cause hang. Code also adds optional debugging output for recursive call that
is compiled only if NDEBUG is not defined.
This code is not 100% thread safe because mesa doesn't include increment and
test atomic operation. There is built-in gcc functions but they are only
available from gcc 4.2.
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NOTE: THIS REQUIRES AN UPDATED DRM!
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Only really got good testing on r500 so far, need to enable in
DDX and play some more.
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this should only really affect DRI2 since we mostly have a surface in DRI1.
I don't think this is perfect yet, but it is a better start than nothing.
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another case of image never matching miptree in case of compressed textures
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- fix not respecting required hardware stride with compressedTexImage -
this fixes #22615.
- make sure correct stride is used in various places
- fix stored miptree never matching with a TexImage call with compressed
texture
- don't always store data with compressedtexsubimage at offset 0,
and actually use the supplied pixel data... (untested)
- make sure rows for compressed texture handling are rounded up not down
Note that trying to access stored compressed textures in hardware miptrees
from core mesa (get_compressed_teximage, swrast fallbacks) can't work correctly,
since RowStride isn't really set to anything useful, plus some places (at least
get_compressed_teximage) assume this data has native stride and no padding.
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(corresponding fix to the intel driver one)
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We need to properly set up a fake bo for the texture override,
so add a new function to radeon_bo_legacy.c. This could probably
be used on radeon/r200/r300 to unify the bo handling for
texture override.
compiz now works :)
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This almost fixes compressed mipmapped textures on r200, though some small
mip levels are still broken.
Leave r300 compressed texture stride as is though afaik it's different
to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride
at same place.
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Reported to fix corruption while dragging an active window by John Bridgman.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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fixes texwrap
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This is in preparation of sharing the fragment program compiler with Gallium:
Compiler code is moved into its own directory and modified so that it no
longer depends on driver structures.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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This fixes problem that glxinfo was reporting r600+ cards as unknown.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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noticed by vehemens on IRC.
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We need to emit a relocation for pitch register so that kernel can
check and properly setup tiling on the color buffer.
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Otherwise simple apps like glxgears pick up a DirectColor visual since the X
server mixes the depth 32 visual in with the other GLX visuals, and this seems
to result in a (mostly) black screen due to a bad ColorMap for a lot of people.
The bad ColorMap may be a bug in the apps, the X server or X driver, and
regardless of that I think the X server should ideally make the depth 32 GLX
visual separate from the rest again, but in the meantime this makes us cope.
(depth_bits is either 16 or 24, never 0)
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patch from Kevin DeKorte with some minor fixes from me.
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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This alleviates the need for an additional symbol.
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tested on r500 with zreaddraw with Z buffer in all 3 modes
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