Age | Commit message (Collapse) | Author |
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By calling radeon_draw_buffers (which sets the necessary flags
in radeon->NewGLState) and revalidating if NewGLState is non-zero
in r200TclPrimitive. This fixes an assert in libdrm (the color-/
depthbuffer was changed but not yet validated) and and stops the
kernel cs checker from complaining about them (when they're too
small).
Thanks to Mario Kleiner for the hint to call radeon_draw_buffer
(instead of my half-broken hack).
v2: Also fix the swtcl r200 path.
Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Remove duplicated includes.
Signed-off-by: Brian Paul <brianp@vmware.com>
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As per discussions at XDS.
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taken from Dave's r600g fix
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This is already covered by radeon_mipmap_tree.c, and my convolution
cleanups broke in the presence of this code. Thanks to Marek Olšák
for tracking down the relevant miptree code for me.
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More optional code.
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Otherwise, when we switch to an indirect glx context and then back, it looks
like we're still current.
https://bugs.freedesktop.org/show_bug.cgi?id=29977#c7
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
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'struct dd_function_table' only conditionally contains
the function pointer NewFramebuffer and friends based on
FEATURE_EXT_framebuffer_* defines. (See src/mesa/main/dd.h)
Fixes the build when the features are disabled and the vfuncs
don't exist.
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This can be supported on r600 without using the endian swapper, and is a
better fit for (typical) uploads using GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV
anyway.
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seems it got lost in commit 0d383547
have no earlier radeons to test, but npot mipmaps were not supported there?
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This is a follow-up patch to commit
f4511c4835879090ce7e6afe3ac26b98fb91899a.
Files that include tnl_dd/t_dd_dmatmp.h now need to also include
m_xform.h as t_context.h no longer includes it.
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Fixes a hardlock.
NOTE: this is a candidate for the 7.8 branch, provided the half float vertex
is really implemented there.
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Needed for the the 2D tiling span functions.
v2: rebase on new kernel, mesa changes
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Requires tiling config ioctl support from the drm to use.
kms only.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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When a DRI2 swap buffer is pending we need to make sure we
have the flush extension so radeon doesn't resume rendering to
or reading from the not yet blitted front buffer.
This fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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This reverts commit 8446f257b3e3ca4a3eb2c79bc357e46343e04e87.
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When DRI2 swap buffer is pending (copy buffer not pageflipping)
we need to make sure we have the flush extension so radeon doesn't
resume rendering on the not yet blitted front buffer.
Modified version of Jerome's patch to add flush extension
in the correct place.
This prepares a possible fix for:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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The extension never worked, the implementation returns GLX_BAD_CONTEXT
when enabling the frame tracking.
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Only r200 implemented it.
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This avoids calling radeonFlush() during context destruction, when
ctx->DrawBuffer would be NULL.
NOTE: This is a candidate for the 7.8 branch.
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fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28771
NOTE: This is a candidate for the 7.8 branch.
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Need to flush command stream before mapping texture image
that is referenced by current cs.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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When searching for valid miptree check images in range
of [BaseLeve, MaxLevel] not [MinLod, MaxLoad].
Prevents unnecessary miptree allocations in cases when during
every rendering operation different texture image level
was selected using MIN_LOD = MAX_LOD = level (for every level
new miptree for whole texture was allocated).
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Always store selected miptree in texObj->mt so get_base_teximage_offset returns correct data.
Found with piglit/mipmap-setup.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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This reverts commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92.
It was based on a failure to understand how ther driver allocates
memory, and causes a regression with Celestia.
Set MaxLevel to dstLevel before allocating new mipmap level.
The radeon driver will fail to allocate space for a new level that
is outside of BaseLevel..MaxLevel. Set MaxLevel before allocating.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Use _mesa_meta_GenerateMipmap. It is Fast Enough(tm).
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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When generating or uploading a new (higher) mipmap level for an image,
we can need to allocate a miptree for a level greater than
texObj->MaxLevel.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This can happen when checking if a software fallback for a higher level
operation (such as GenerateMipmap) is needed.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Conflicts:
src/mesa/drivers/dri/common/dri_util.h
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bo_legacy->tobj cannot be NULL before the call to driUpdateTextureLRU.
There is a NULL check earlier in the routine, and if bo_legacy->tobj is
NULL, memory is allocated.
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Although these cards have 2 pipelines on the silicon only
the first passed the QA and the other should be disabled.
http://www.digital-daily.com/video/ati-radeon9800se/
http://www.rojakpot.com/showarticle.aspx?artno=101&pgno=1
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
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Add a new DRI2 configuration query extension. Allows for DRI2 client
code to query for common DRI2 configuration options.
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Declaring the loop index inside for () is not supported by this version.
Signed-off-by: Brian Paul <brianp@vmware.com>
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This should be drmCommandWriteRead to avoid an EINVAL error on systems
that strictly check ioctl args. This command has been r/w for ever.
Discussion with airlied agreed that this was the correct course.
Signed-off-by: Brian Paul <brianp@vmware.com>
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