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Otherwise simple apps like glxgears pick up a DirectColor visual since the X
server mixes the depth 32 visual in with the other GLX visuals, and this seems
to result in a (mostly) black screen due to a bad ColorMap for a lot of people.
The bad ColorMap may be a bug in the apps, the X server or X driver, and
regardless of that I think the X server should ideally make the depth 32 GLX
visual separate from the rest again, but in the meantime this makes us cope.
(depth_bits is either 16 or 24, never 0)
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patch from Kevin DeKorte with some minor fixes from me.
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into r6xx-rewrite
This builds, but I get an assertion in radeonGetLock() due to
the drawable being null.
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This alleviates the need for an additional symbol.
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tested on r500 with zreaddraw with Z buffer in all 3 modes
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this uses the correct formula for macro tiled buffers for readback
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since the surfaces aren't linear you can't just use GET_PTR
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This allows double buffered apps to run, but perfomance
will be awful until we implement something faster.
You must update to the latest kernel modules.
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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This function takes a GLint not a GLuint, passing in -1
breaks internally.
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Fixes those formats in fbo_firecube.
Only tested with r300, radeon and r200 compile tested only.
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Fixes fgl_glxgears and progs/demos/fbotexture after pressing 'c'.
Tested with r300, radeon and r200 compile tested only.
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Port fixes to read buffer from front.
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Need to retrieve the bits from the rrb not from screen struct
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The _Enabled field isn't updated at the point that DrawBuffers is called,
and the Driver.Enable() function does the testing for stencil buffer
presence anyway.
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It is possible to bind texture images of an incomplete mipmapped texture.
Software fallbacks in this case incorrectly tried to mmap the entire texture.
Additionally, add span functions for 1555 and 4444 formats.
This fixes crashes in piglit's fbo-readpixels test; unfortunately, the test
itself still fails - this needs to be investigated.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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This updates some of the clear code from Intel gives a 5x clearspd perf
for me here. played openarena also, not sure if the viewport changes
broke anything,
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it might still be misrendering not sure
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fgl_glxgears -fbo runs, though the gears don't look right yet.
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make sure to turn off when no texture is used in hw
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Can be used for buffer swap as well.
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texture bo setup isn't quite working yet
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This moves a big chunk of the space checking code into libdrm so
it can be shared by the DDX.
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Fixes fighting between GPU and software rendering with TTM.
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half stealing the code without taking the intel regions
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I suspect this might break TFP in some way but it makes firecube run here
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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This reverts commit 0952645fe04a27968565ea4d913500c23b1b11e3.
Need to revisit where this is going wrong
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This fixes an assertion in glReadPixels from the front buffer.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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This allows us to return the unused portion of the dma buffer
to the allocator instead of wasting nearly 16k a pop.
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still always enable max, but the right values this time.
More work should probably be done for saner limits without mm, and/or
dri conf option allow_large_textures (which is ignored) removed.
3D limit on r100 is pretty arbitrary as still handled by swrast anyway.
Also fix r300 limits (except 3d I've no idea what the max is anyway so
keep using mesa default).
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This was already correct in the GEM code
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need to pass target parameter to radeon_teximage/radeon_subteximage functions
otherwise mipmap generation for cube maps can't work (assert/segfault in
_mesa_generate_mipmap)
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drm cmd checker would refuse cube emits
also fix an issue in the cs path which would calculate the register
offset off by one dword.
Only same testing done as original code (none except compile tested).
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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if its on the list its on the list don't go readding it.
multitexturing from the same texture could cause this.
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We flush the command buffer so we don't emit mixed
state (with new and previous buffer size) command
buffer, this is especialy affecting zbuffer states.
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