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path: root/src/mesa/drivers/dri
AgeCommit message (Expand)Author
2010-06-08intel: Remove the non-gem paths for batchbuffer upload.Eric Anholt
2010-06-08intel: Update comment in intel_tex_copy from before miptree x/y rework.Eric Anholt
2010-06-08r600: Make next_inst() static.Henri Verbeet
2010-06-08r600: Assert output registers have a valid export index.Henri Verbeet
2010-06-08r600: Process exports for all written fragment outputs.Henri Verbeet
2010-06-08r600: Fill uiFP_OutputMap for all written fragment outputs.Henri Verbeet
2010-06-05r300compiler: fix scons buildJoakim Sindholt
2010-06-05i915: Only emit a MI_FLUSH when the drawing rectangle offset changes.Chris Wilson
2010-06-05i915: Fix off-by-one for drawing rectangle.Chris Wilson
2010-06-05i915: Inhibit render cache flush when changing drawing rectangle offset.Chris Wilson
2010-06-05r300/compiler: implement SIN+COS+SCS for vertex shadersMarek Olšák
2010-06-05r300/compiler: implement SNE unwound for r3xx VS, natively for r5xx VSMarek Olšák
2010-06-05r300/compiler: implement SEQ unwound for r3xx VS, natively for r5xx VSMarek Olšák
2010-06-05r300/compiler: implement SFL for vertex shadersMarek Olšák
2010-06-04i915: Don't use XRGB8888 on 830 and 845.Eric Anholt
2010-06-04i915: Clamp minimum lod to maximum texture level too.Eric Anholt
2010-06-04intel: Fix intel_compressed_num_bytes for FXT1 after I broke it.Eric Anholt
2010-06-03r300/compiler: print opcode names instead of numbersMarek Olšák
2010-06-02dri/swrast: Remove unnecessary header.Vinson Lee
2010-06-02intel: Remove a leftover DRI1/DRI2 conditionalKristian Høgsberg
2010-06-01intel: Fallback to meta if we're asked to CopyTexImage2D from RGB to RGBAKristian Høgsberg
2010-05-31swrast: add TFP support to swrast.Dave Airlie
2010-05-31gallium: fix TFP on galliumDave Airlie
2010-05-31intel: Initialize batch->reserved_space on allocationChris Wilson
2010-05-29r300: fix blits for textures of width/height greater than 2048 on r5xxMarek Olšák
2010-05-28i965: Add cache unit -> bo name mapping for more gen6 state objects.Eric Anholt
2010-05-28i965: fix PIPE_CONTROL command for gen6.Zou Nan hai
2010-05-26Enable hardware mipmap generation for radeon.Will Dyson
2010-05-26Fix image_matches_texture_obj() MaxLevel checkWill Dyson
2010-05-26Fallback to software render if there is no miptree for an imageWill Dyson
2010-05-26i965: Add support for EXT_timer_query on Ironlake.Eric Anholt
2010-05-26intel: Handle decode of PIPE_CONTROL instructions.Eric Anholt
2010-05-26i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.Eric Anholt
2010-05-26i965: Don't PIPE_CONTROL instruction cache flush.Eric Anholt
2010-05-26i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.Eric Anholt
2010-05-26r300/compiler: implement SGT+SLE opcodesMarek Olšák
2010-05-26r300/compiler: fix dumping r5xx vertex shadersMarek Olšák
2010-05-26r300/compiler: move hardware caps to the radeon_compiler base structMarek Olšák
2010-05-26r300/compiler: shorten swizzle expressionsMarek Olšák
2010-05-23i965: Add support for all 8 possible ARB_draw_buffers in Mesa.Eric Anholt
2010-05-23i965: Fix bit allocation for number of color regions for ARB_draw_buffers.Eric Anholt
2010-05-20i965: remove disabled code for cycling through MRF registers in clipping.Eric Anholt
2010-05-20intel: Throttle after doing copyregion/swapbuffers round tripKristian Høgsberg
2010-05-19r300/compiler: Implement constant foldingNicolai Hähnle
2010-05-19r300/compiler: Emit 0.5 swizzle when necessary.Tom Stellard
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt
2010-05-18i965: Revert accidental debug change in 562e2d114ec0cba8Eric Anholt
2010-05-18 gen6 fix: fix a wrong bit in binding_table_pointerZou Nan hai
2010-05-17i965: Fix point coordinate replacement after airlied's ffvertex changes.Eric Anholt
2010-05-17i965: Add SF program disasm under INTEL_DEBUG=sf.Eric Anholt
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