Age | Commit message (Collapse) | Author |
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so r200SetBuffer, r200SpanRenderStart and r200SpanRenderFinish get called again.
Bugzilla #3705, #3706.
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either with software or hardware rendering.
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by Idr. This patch is based on Idr patch to radeon driver.
Change #if 1 to #if 0 (r300_context.c:l69) for old dispatch
tab.
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Remove old (pre-renderbuffer) span code instead of converting that too. Remove this old code from mach64 (the dead code was not fully converted to spantmp2 previously) too.
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individual drivers and put them in common code. It is still possible for a driver to define its own macros if it has special needs. This affects CLIPPIXEL, CLIPSPAN, HW_CLIPLOOP, HW_ENDCLIPLOOP, and for drivers using the spantmp2 template also GET_SRC_PTR and GET_DST_PTR.
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device-specific code. A new Python script
(src/mesa/glapi/extension_helper.py) generates a list of all
entry-points for all known extensions. Each driver the selects only
the extensions that it needs and enables the via either
driInitExtensions or driInitSingleExtension.
This code has been compile-tested on a drivers, but has only been
run-tested on mga and i915 (on i830 hardware).
These changes were discussed at length on the mesa3d-dev mailing list.
http://marc.theaimsgroup.com/?t=111947074700001&r=1&w=2
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-use depth tiling if tiling is enabled
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Fix slipup from CVS update that was commented out and did not show up during compilation.
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Emit wait idle and pacify r300 before emitting state - this seems to improve stability.
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If that stuff is still needed, lots of other updates are needed anyway.
Also, some misc MALLOC/FREE -> _mesa_malloc/free() changes.
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during fallbacks. In one case, _swsetup_Wakeup had just been called, covering
the need there, and in the other case, we can simply exit the entire
radeonChooseVertexState function, knowing that it will be called again once we
leave the fallback.
Bugzilla #: 2516
Submitted by: sroland
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RADEON_DEBUG=fall.
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values to reserved fields on the card, resulting in all-black output and
sometimes hangs.
Submitted by: Thomas Winischhofer
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Depth tiling breaks software fallbacks and depth buffer reads.
radeon_span.c **must** be updated for anything that is related to tiling.
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The driver appears to work reliably (i.e. lockup-free) with a card based
on this chip. However, I have not explored whether we could get anything
in terms of 3D performance "for free" just by setting some magic bits
in those registers that are still a mystery to us.
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They are relative to the card's address space, not relative to fbLocation,
which will be important once we program MC_FB/AGP_LOCATION in the way
they are programmed on older Radeon chips.
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This patch makes use of two of the new ioctls added in MGA DRM version
3.2. Specifically, the DRM_MGA_SET_FENCE and DRM_MGA_WAIT_FENCE
ioctls are used in mgaWaitForFrameCompletion. As a result the MMIO
register region and the primary DMA region are *not* mapped (if DRM
3.2 is available).
This patch does *not* make use of the new get_param query was added to
differentiate between G4x0 cards and G550 cards. That is left to a
future update.
Xorg bug: 3259
Reviewed by: Eric Anholt
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- Calculate tc_count in EmitArrays (enabled units != nr texcoords).
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Use SRC0A instead of WZY/XXX combination for W in XYZ positions.
Remove dodgy hack from POW opcode, now works correctly without it
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as other drivers.
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of GL_RGBA in driNewRenderbuffer of the backbuffer.
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than it helps, and we seem to have a handle on how to fix it.
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some cleanups on the span macros. This does not deal with the brokenness of
depth spans, but makes the code more readable.
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remove those descriptions and the corresponding bits on r200, where they're no
longer used.
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about 200 lines from the code and 25k from the binary, while matching other
drivers more closely. In the worst case (tcl_mode=0) it appears to have
a performance cost of 4.4% +/- 0.3% on quake3 (800x600 demofours, 1ghz p3,
rv200). Tested on ut2004, ut, q3, projtex.
Submitted by: Andreas Stenglein <a.stenglein@gmx.net>
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