| Age | Commit message (Collapse) | Author |
|---|
|
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
|
|
We were asking for something illegal (write_domain != 0 && read_domains !=
write_domain) because at the time of writing the region surfaces were used
for texturing occasionally as well, and we weren't really clear on the model
GEM was going to use.
This reliably triggered a kernel bug with domain handling, resulting in
oglconform mustpass.c failure. Of course, it only became visible after
01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing.
|
|
GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
|
|
Note that I24X8 vs. A24X8 vs. L24X8 doesn't seem to make any difference
for texture/shadow compare, however.
|
|
|
|
|
|
|
|
|
|
Fixes mysterious failures in glean glsl1 test.
|
|
|
|
This is a 2% win in fbo_firecube, and would avoid a sw fallback for
masked clears.
|
|
Noticed this with the fbotexture demo.
|
|
|
|
The default for EmitCondCodes got flipped when gallium-0.2 was merged.
This fixes GLSL if/else/endif regressions.
Drivers that use GLSL should always explicitly set the flag to be safe.
|
|
R3xx/R5xx fragment program texture constants must come from a hardware
register instead of the constant file, so we redirect if necessary during
the native rewrite phase.
The symptoms of this bug started appearing when the Mesa fixed function
texenvprogram code started using STATE_CURRENT_ATTRIB constants for
texture coordinates when the corresponding attributes were constant across
all vertices.
Signed-off-by: Nicolai Haehnle <nhaehnle@gmail.com>
|
|
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
|
|
This doesn't effect correctness, but we were emitting an extraneous ADD.
|
|
|
|
|
|
|
|
|
|
It's done in the Mesa GLSL compiler. The only part of it that might
matter in drivers is the centroid sampling option for MSAA.
|
|
|
|
|
|
|
|
|
|
While running conform with render-to-texture:
conform -d 33 -v 2 -t -direct
the i965 driver failed this assertion:
intel_clear.c:77: intel_clear_tris: Assertion `(mask & ~((1 << BUFFER_BACK_LEFT) | (1 << BUFFER_FRONT_LEFT) | (1 << BUFFER_DEPTH) | (1 << BUFFER_STENCIL))) == 0' failed.
The problem is that intel_clear_tris() is called by intelClear() to
clear any and all of the available color buffers, but intel_clear_tris()
actually only handles the back left and front left color buffers; so
the assertion fails as soon as you try to clear a non-standard color
buffer.
The fix is to have intelClear() only call intel_clear_tris() with
buffers that intel_clear_tris() can support. intelClear() already backs
down to _swrast_Clear() for all buffers that aren't handled explicitly.
|
|
This involved fixing driConcatConfigs to not return const (which had made a
mess of a previous patch too).
|
|
|
|
|
|
|
|
Everything other than "make sure the last rendering ends up visible on the
screen" doesn't need that behavior.
|
|
|
|
Found while debugging cairo-gl.
|
|
|
|
This is the big merge of the gallium-0.2 branch into master.
gallium-master-merge was just the staging area for it.
Both gallium-0.2 and gallium-master-merge are considered closed now.
Conflicts:
progs/demos/Makefile
src/mesa/main/state.c
src/mesa/main/texenvprogram.c
|
|
|
|
Add the MSAA samples array or make sure its contents are initialized.
|
|
Fixes bad background in all the progs/glsl/ tests.
|
|
(cherry picked from commit f7d80aa00611917bc8ce637136d982b151b8f44f)
This also involved adding the new MSAA fields to driCreateConfigs().
Also, re-add prog_instructions->Sampler field for i965 driver. Will
have to revisit that.
|
|
Merge commit 'origin/gallium-0.2' into gallium-master-merge
Conflicts:
Makefile
docs/relnotes-7.4.html
docs/relnotes.html
src/mesa/drivers/dri/i965/brw_wm.h
src/mesa/main/imports.c
src/mesa/main/mtypes.h
src/mesa/main/texcompress.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
src/mesa/vbo/vbo_exec_api.c
src/mesa/vbo/vbo_save_draw.c
|
|
this path isn't enabled by default in any case.
|
|
The MI opcodes have different variable length masks, so use an operand
specific mask to decode the length.
|
|
A couple of minor typos that proclaimed an error in the wrong command, and
failed to offset the mask.
|
|
By selecting a 4444 texture format due to a bad test, we hit the
intel_update_wrapper error path, and despite the appearance of error handling
in it and its callers, the desired behavior (software fallback) doesn't occur.
|
|
|
|
|
|
Too much commit -a while debugging.
|
|
This lets swrast produce an fbconfig suitable for the root visual now that
the server's not allowing mismatched fbconfigs.
|
|
|
