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path: root/src/mesa/drivers/dri
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2008-12-18i915: fix abort issue. (bug #19147)Xiang, Haihao
2008-12-15intel: stub out CompressedTexSubImage2D instead of segfaulting.Eric Anholt
2008-12-15i965: Update state before checking for fallbacks in brw_try_draw_prims.Eric Anholt
This got flipped around in 7855b2aef6bd9e9c2d73260b5cd166159b2525c6. Bug #18907. Thanks to idr for pointing me at a nicer testcase than blender.
2008-12-14intel: Don't steal renderbuffer from caller in intel_miptree_create_for_regionPierre Willenbrock
Fixes double-frees of some regions, once from the renderbuffer code and once from the miptree itself. Bug #19062
2008-12-14i965: Add decode of index/vertex buffer and primitive emit.Eric Anholt
2008-12-14intel: Add batchbuffer assertions to hopefully catch future mistakes.Eric Anholt
2008-12-14Add more package metadata to the pkg-config filesDan Nicholson
The pkg-config files have been filled in more thoroughly to allow users to use mesa more effectively. By adding metadata to Requires.private, Libs.private and Cflags, we can ensure that all the libraries and headers will be found in all situations. However, the full substitutions are only done when using the configure script. This also fixes the glu pkg-config file to account for using GL or OSMesa. Fixes bug 18161.
2008-12-13i965: Finish OPCODE_NOISEn instructions.Gary Wong
Added missing OPCODE_NOISE4, and use BRW_REGISTER_TYPE_D (instead of _UD) in the initial RNDD instructions (which avoids saturating negative inputs to 0).
2008-12-12intel: check for null texture. (fix #13902)Xiang, Haihao
2008-12-11i915: fallback for cube map texture.Xiang, Haihao
The i915 (and related graphics cores) only support TEXCOORDMODE_CLAMP and TEXCOORDMODE_CUBE when using cube map texture coordinates, so fall back to software rendering for other modes to avoid potential gpu hang issue. This fixes scorched3d issue on 945GM(see bug 14539).
2008-12-08intel: Require the right amount of space in glBitmap blit acceleration.Pierre Willenbrock
This leads to problems when the batchbuffer is flushed, but the bitmap data could not fit into it.
2008-12-06intel: Fall back on rendering to a texture attachment with a border.Eric Anholt
Fixes a segfault in oglconform fbo.c test.
2008-12-06intel: Fix crash in automatic mipmap generation for glCopyTex{Sub,}Image.Eric Anholt
The images aren't mapped at this point, so we want the generic Mesa path for GenerateMipmapEXT that does the mapping/unmapping for us. Ideally Mesa would just call it for us.
2008-12-06intel: Fix glCopyPixels blit acceleration for FBO destinations.Eric Anholt
This was another opportunity to either get clipped to screen size or not get clipped enough and draw outside of object boundaries.
2008-12-06intel: Fix glBitmap blit acceleration for FBO destinations.Eric Anholt
Bug #18914. Fixes fbo_firecube hang due to drawing outside the FBO bounds. Thanks to Pierre Willenbrock for debugging the issue.
2008-12-06intel: Put CopyTexImage fallback under DEBUG_FALLBACKS not DEBUG_TEXTURE.Eric Anholt
2008-12-03i965: Fix failure to upload new constant data when changing programs.Eric Anholt
This is fallout from the ffvertex_prog.c work. It doesn't call ProgramStringNotify, so we don't set param_state, so we wouldn't track when VP parameters changed, and constants wouldn't get uploaded. Instead, remove param_state entirely and just use the real value that we want to be tracking. Fixes rendering in openarena since BRW_NEW_BATCH got disentangled from BRW_NEW_INDICES. Bug #18822.
2008-12-03i965: Fix stray character that the compile whined about.Eric Anholt
2008-12-02intel: restore old vertex submit paths for i8xx hardware.Dave Airlie
Intel docs state that only 830/845 have VBOs, 855/865 don't. So lets just not use them on i8xx at all. This restores the old pre-vbo code and uses it on all 8xx hw.
2008-11-28i965: Add a new state flag BRW_NEW_NR_SURFACES instead of CACHE_NEW_SURFACEEric Anholt
The CACHE_NEW_SURFACE bit always gets spammed since we get many different surface BOs per state emit, but the only consumer of it wanted to just know how many surfaces were enabled.
2008-11-28i965: Fix clashing enums for BRW_NEW_INDICES/VERTICES versus BATCH/DEPTH_BUFFER.Eric Anholt
Fixes upload of large amounts of state for every new primitive emit.
2008-11-28i965: Remove BRW_WM_LOCK dirty bit, introduced to work around lack of relocs.Eric Anholt
This was causing a prepare of wm state at every primitive emit.
2008-11-28i965: Add debug code for dumping how frequently different dirty bits are set.Eric Anholt
2008-11-28i915: Remove dead early z enable bit which was always on.Eric Anholt
2008-11-28i965: Reduce fast-pathiness of brw_try_draw_prims, bringing in important checks.Eric Anholt
Later primitives, even if they caused a full state validate, wouldn't check that there was enough space in the batchbuffer, occasionally triggering the sanity check. We also skipped the aperture space check, even if it would mean bringing in new programs and associated state.
2008-11-21i965: Add support for accelerated CopyTexSubImage.Eric Anholt
There were hacks in EmitCopyBlit before to adjust offsets so that y=0 after the offsets had been adjusted for a negative pitch. It appears that those hacks were due to an unclear and surprising aspect of the hardware: inverting the pitch results in the blit into the specified rectangle being inverted, without the user needing to adjust y and base offset. Tested with piglit copytexsubimage test on 915GM and GM965. Should fix serious performance issues with ETQW and other applications.
2008-11-21intel: Don't glBitmap fallback with scissoring enabled.Eric Anholt
The blit bitmap code already handles scissoring. This is a 15-100% speedup on blender benchmark.blend thanks to avoiding fallbacks. Bug #17951.
2008-11-21i915: Don't overwrite i915's Viewport function from generic code.Eric Anholt
Instead, have i965 and i915 both call the generic function from their Viewport.
2008-11-20intel: fix i830 comment + backwards VB offsets.airlied
According to Keith the docs have these offsets the other way around
2008-11-20intel: fix i8xx vbo enable bitairlied
2008-11-20intel: add lots of i830 engine to intel_decode debugairlied
2008-11-12i965: Upload state on primitive switch, don't just prepare it.Eric Anholt
This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
2008-11-12i965: Fix VB refcount leak on aperture overflow.Eric Anholt
2008-11-12i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt
As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
2008-11-12i965: Fix up SF max_threads.Eric Anholt
We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
2008-11-12i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt
The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
2008-11-12i965: Update WM maximum threads for G4X.Eric Anholt
2008-11-12i965: Add a big comment explaining my understanding of URB management.Eric Anholt
It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
2008-11-11intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao
This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
2008-11-10mesa: restore glapi/ prefix on #includeBrian Paul
2008-11-10GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul
See bug 18445. When getting array results, __glXReadReply() always reads a multiple of four bytes. This can cause writing to invalid memory when 'n' is not a multiple of four. Special-case the glAreTexturesResident() functions now. To fix the bug, we use a temporary buffer that's a multiple of four bytes in length. NOTE: this commit also reverts part of commit 919ec22ecf72aa163e1b97d8c7381002131ed32c (glx/x11: Added some #ifdef GLX_DIRECT_RENDERING protection) which directly edited the indirect.c file rather than the python generator! I'm not repairing that issue at this time.
2008-11-10dri: alloc __DRIscreen object with calloc()Brian Paul
2008-11-06mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul
Trunc is a more accurate description; there's no type conversion involved.
2008-11-06i965: Always check vertex program.Xiang, Haihao
Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
OPCODE_NOISE4 coming later.
2008-11-02i965: Clean up stale NDC comment.Eric Anholt
2008-11-02i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt
This cuts one MOV out when setting a zero header.
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
2008-11-02i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt
Also, add a comment explaining what brw->urb.constrained tries to do.
2008-11-01Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard
Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com>