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path: root/src/mesa/drivers/dri
AgeCommit message (Expand)Author
2009-11-10i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt
2009-11-10i965: Add a note explaining the data cache domain.Eric Anholt
2009-11-10i965: Unalias src/dst registers for SGE and friends.Eric Anholt
2009-11-10i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt
2009-11-09r600/r700: typo, fix mask of DB_ALPHA_TO_MASKJerome Glisse
2009-11-09r600: rework DB render setupAlex Deucher
2009-11-09r600: don't emit htile regsAlex Deucher
2009-11-09r600: add missing ZPASS setup bits for r7xx+Alex Deucher
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
2009-11-06i965: Collect GLSL src/dst regs up in generic code.Eric Anholt
2009-11-06intel: better front color buffer test in intelClear()Brian Paul
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
2009-11-06intel: Finish removing the fallback code for bug #16697.Eric Anholt
2009-11-06intel: Don't validate in a texture image used as a render target.Eric Anholt
2009-11-06intel: Clean up some extra struct indirection in finalize.Eric Anholt
2009-11-06intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt
2009-11-06intel: Remove duplicated arguments from intel_miptree_match_image().Eric Anholt
2009-11-06i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt
2009-11-06intel: Remove obsolete comment about GEM in the spans code.Eric Anholt
2009-11-06intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt
2009-11-06Make a convenient int for what chipset generation we're on.Eric Anholt
2009-11-06intel: call intel_check_front_buffer_rendering() in intelClear()Brian Paul
2009-11-04r600: rework draw functionsAlex Deucher
2009-11-04r600: fix count prediction for IB caseAlex Deucher
2009-11-04Fix YTILE spantmp functionsAlan Hourihane
2009-11-03Merge branch 'mesa_7_6_branch'Brian Paul
2009-11-03intel: avoid unnecessary front buffer flushing/updatingBrian Paul
2009-11-02r600: implement LOG op in compilerPierre Ossman
2009-11-02r600: implement EXP op in compilerPierre Ossman
2009-10-31radeon: add missing includeDave Airlie
2009-10-31radeon: use _mesa_get_current_tex_unitDave Airlie
2009-10-30intel: Use GTT mapping when available for swrast.Eric Anholt
2009-10-30intel: Fix up z24_x8 depth spans since the texformat merge.Eric Anholt
2009-10-30i965: Add an index assert on get_fp_inst array like other compiler arrays.Eric Anholt
2009-10-30i965: Fix BRW_WM_MAX_INSN to reflect current limits.Eric Anholt
2009-10-30intel: Set the texture format in the TFP path.Eric Anholt
2009-10-30r600: remove duplicate lineAlex Deucher
2009-10-30r600: fill in some missing tex formatsAlex Deucher
2009-10-30r600: fix a warning, update commentsAlex Deucher
2009-10-30r600: use AUTO_INDEX for draw - saves cmd buffer spaceAndre Maasikas
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