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2009-09-10Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-10intel: disable intel_stencil_drawpixels() for nowBrian Paul
It doesn't work reliably even when all the prerequisite checks are made.
2009-09-10Fix merge failIan Romanick
One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <brianp@vmware.com> Date: Wed Sep 9 08:33:39 2009 -0600
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/drivers/dri/intel/intel_context.c
2009-09-10i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
2009-09-10intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
2009-09-10intel: Don't forget to map the depth read buffer in spans.Eric Anholt
This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
2009-09-10r300: enable rb3d_discard_src_pixel_lte_threshold for more chips on dri2Alex Deucher
2009-09-10r300: add full support for two sided stencil on r5xx for dri2Alex Deucher
2009-09-10radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen
Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
2009-09-09i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254
2009-09-09radeon: Add more verbose error message for failed command buffer.Pauli Nieminen
2009-09-09i965: fix an overlooked merge conflictBrian Paul
2009-09-09r600: check if textures are actually enabled before submissionAlex Deucher
noticed by taiu on IRC.
2009-09-09Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-09r600: fix ftp for dri1Alex Deucher
We use t->bo for dri1 since r600 uses CS for dri1.
2009-09-09intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2009-09-09r600: don't setup hardware state if TFPDave Airlie
if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon
2009-09-08intel: Add support for ARB_draw_elements_base_vertex.Eric Anholt
On the 965, we just drop the value into the primitive packet. On non-945, we rely on the sw tnl code handling it.
2009-09-08mesa: Add support for ARB_draw_elements_base_vertex.Eric Anholt
2009-09-08glapi: Add ARB_draw_elements_base_vertexEric Anholt
2009-09-08mesa: Expose NV_depth_clamp if ARB_depth_clamp is supported.Eric Anholt
The wording of these two is exactly the same, except for the issue "Can fragments with wc<=0 be generated when this extension is supported?", which idr thinks is a non-issue for us.
2009-09-08i965: Add support for ARB_depth_clamp.Eric Anholt
2009-09-08mesa: Add support for ARB_depth_clamp.Eric Anholt
This currently doesn't include fixing up the cliptests in the assembly paths to support ARB_depth_clamp, so enabling depth_clamp forces the C path.
2009-09-08i965: Respect spec requirement for pixel shader computed depth with no zbuffer.Eric Anholt
2009-09-08i965: Set NULL WM surfaces as tiled according to requirement by specs.Eric Anholt
2009-09-08i965: Use the renderbuffer surface size instead of region size for WM surfaces.Eric Anholt
For drawing to lower mipmap levels, the region size makes the renderbuffer be the size of the lowest level, instead of the current level. On DRI1, Brian previously found that the RB size was incorrect, so leave this broken there.
2009-09-08Revert "intel: helper to debug bufmgr (disabled)"Eric Anholt
This reverts commit e0ec405a9fa6fbc1cf2ac531ed5efd1a64e01f18. This is already available in INTEL_DEBUG=bufmgr in the environment.
2009-09-08i965: #include clean-upsBrian Paul
2009-09-08intel: #include clean-upsBrian Paul
2009-09-08i965: use _mesa_is_bufferobj()Brian Paul
Also, remove unneeded call to _mesa_validate_pbo_access(). It's done by core Mesa as the comment suggested.
2009-09-08i965: use _mesa_is_bufferobj()Brian Paul
2009-09-08i965: use _mesa_is_bufferobj()Brian Paul
2009-09-08i965: use _mesa_is_bufferobj()Brian Paul
2009-09-08r600: fix dri2 clippingAlex Deucher
2009-09-08i965: fix incorrect test for vertex position attributeBrian Paul
2009-09-04r600: add support for EXT_texture_sRGBAlex Deucher
2009-09-04r300: Add support for GL_EXT_provoking_vertexAlex Deucher
2009-09-04r600: Add support for GL_EXT_provoking_vertexAlex Deucher
2009-09-04i965: Fix warnings in intel_pixel_read.c.Eric Anholt
(cherry picked from commit c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)
2009-09-04intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
(cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
2009-09-04intel: Update Mesa state before span setup in glReadPixels.Eric Anholt
We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
2009-09-04intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt
(cherry picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)
2009-09-04i965: Don't set the complete field when there is more VUE yet to come.Eric Anholt
This should help with things like lightsmark, but I don't have a testcase for this commit.
2009-09-04i965: Add support for 2 threads in the GS.Eric Anholt
This brings noop vertex shader throughput from 6.8M verts/sec to 10.4M verts/sec using GL_QUADs on my GM45.
2009-09-04i965: Add support for KIL_NV in brw_wm_emit.cEric Anholt
I ran into this lack of support when writing a shader that always discarded the fragments.
2009-09-04i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
(cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
2009-09-04intel: Align cubemap texture height to its padding requirements.Eric Anholt
(cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
2009-09-04intel: Align untiled region height to 2 according to 965 docs.Eric Anholt
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
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