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path: root/src/mesa/drivers/dri
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2010-07-15radeon: allow driconf vblank settings with dri2Alex Deucher
fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28771 NOTE: This is a candidate for the 7.8 branch.
2010-07-14r300/compiler: fix swizzling in the transformation of Abs modifiersMarek Olšák
2010-07-13r300/compiler: implement the Abs source operand modifier for vertex shadersMarek Olšák
2010-07-13r300/compiler: emulate SIN/COS/SCS in r3xx-r4xx vertex shadersMarek Olšák
Despite the docs, the corresponding hardware instructions are r5xx-only.
2010-07-12Merge branch 'master' of git://anongit.freedesktop.org/mesa/mesaMaciej Cencora
2010-07-12r600: Fix include recursion.Vinson Lee
Fix r600_context.h -> r700_oglprog.h -> r600_context.h include recursion.
2010-07-12radeon: fix some wine d3d9 testsMaciej Cencora
Need to flush command stream before mapping texture image that is referenced by current cs. Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11radeon: lower texture memory consumption is some casesMaciej Cencora
When searching for valid miptree check images in range of [BaseLeve, MaxLevel] not [MinLod, MaxLoad]. Prevents unnecessary miptree allocations in cases when during every rendering operation different texture image level was selected using MIN_LOD = MAX_LOD = level (for every level new miptree for whole texture was allocated). Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11radeon: fix teximage migration failure in rare caseMaciej Cencora
Always store selected miptree in texObj->mt so get_base_teximage_offset returns correct data. Found with piglit/mipmap-setup. Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11r300c: Fix vertex data setup for named buffer objects with unaligned offsetMaciej Cencora
Candidate for 7.8 branch Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11r600: Remove unnecessary headers.Vinson Lee
2010-07-10r600: Fix GCC 'implication declaration of function' warnings.Vinson Lee
Fix GCC 'implicit declaration of function' compiler warnings resulting from commit 00fb58ed5d7104e675fe48d84e5049e5f7dbb9d7.
2010-07-09r600: Remove unnecessary header.Vinson Lee
Fixes r600_emit.h -> r600_cmdbuf.h -> r600_emit.h include recursion.
2010-07-09r600: Fix include recursion.Vinson Lee
r700_chip.h included r600_context.h, which included r700_chip.h. Remove the unnecessary r600_context.h inclusion and add missing headers.
2010-07-09mesa: Move [UN]CLAMPED_FLOAT_TO_UBYTE from imports.h to macros.h.Vinson Lee
The other similar integer/float conversion macros are in macros.h.
2010-07-08r300/compiler: Add a register rename pass.Tom Stellard
This pass renames register in order to make it easier for the pair scheduler to group TEX instructions together. This fixes fdo bug #28606
2010-07-08r300/compiler: Fix scheduling of TEX instructions.Tom Stellard
The following instruction sequence will no longer be emitted in separate TEX blocks: 0: TEX temp[0].xyz, temp[1].xy__, 2D[0]; 1: TEX temp[1].xyz, temp[2].xy__, 2D[0]; This fixes fdo bug #25109
2010-07-08i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
When EU executes 'wait' instruction, it stalls and sets notification register state. Host can issue MMIO write to clear notification register state to allow EU continue on executing again. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-07-08i965: Fix disasm of a SEND's mlen and rlen on Ironlake.Eric Anholt
2010-07-08i965: Add decode for Sandybridge DP write messages.Zhenyu Wang
2010-07-08i965: Add definitions for Sandybridge DP write/read messages.Zhenyu Wang
2010-07-08intel: Update intel_decode.c from intel-gpu-tools.Eric Anholt
This came from commit cf255e382d147fe3ca450f0dcec3525190e7dcbc
2010-07-07r600: workaround 3 comp GL_SHORT vertex attribute format on r700Andre Maasikas
guess it's a hw errata?
2010-07-06r300/compiler: Implement KILP opcode.Tom Stellard
Signed-off-by: Marek Olšák <maraeo@gmail.com>
2010-07-03r300/compiler: Fix loop unrollingTom Stellard
2010-07-03r300/compiler: Use hardware flow control instructions for loops on r500.Tom Stellard
2010-07-03r300/compiler: Don't continue copy propagation inside loops.Tom Stellard
2010-07-03r300/compiler: Print debug info for flow control instructions.Tom Stellard
2010-07-03r300/compiler: Enable hardware IF statements for r500 cards.Tom Stellard
2010-07-03r300/compiler: In the peephole optimizer, ELSE should mark the end of aTom Stellard
block.
2010-07-03r300/compiler: Correctly calculate the max number of iterations for loops.Tom Stellard
2010-07-03r300/compiler: Handle loops in deadcode analysis.Tom Stellard
This also allows us to split the loop emulation into two phases. A tranformation phase which either unrolls loops or prepares them to be emulated, and the emulation phase which unrolls remaining loops until the instruction limit is reached. The second phase is completed after the deadcode analysis in order to get a more accurate count of the number of instructions in the body of loops.
2010-06-23Merge branch 'shader-file-reorg'Brian Paul
1. Move all GL entrypoint functions and files into src/mesa/main/ This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits that were in src/mesa/shader/ 2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth 3. Rename src/mesa/shader/ to src/mesa/program/ since all the remaining files are concerned with GPU programs. 4. Misc code refactoring. In particular, I got rid of most of the GLSL-related ctx->Driver hook functions. None of the drivers used them. Conflicts: src/mesa/drivers/dri/i965/brw_context.c
2010-06-23r300/compiler: allow 1024 instructions in r5xx vertex shadersMarek Olšák
2010-06-23r300/compiler: allow 32 temporaries in vertex shadersMarek Olšák
2010-06-23r300/compiler: emulate loops in vertex shadersMarek Olšák
It is not perfect, but it is the best we got.
2010-06-19Revert "Fix image_matches_texture_obj() MaxLevel check"Will Dyson
This reverts commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92. It was based on a failure to understand how ther driver allocates memory, and causes a regression with Celestia. Set MaxLevel to dstLevel before allocating new mipmap level. The radeon driver will fail to allocate space for a new level that is outside of BaseLevel..MaxLevel. Set MaxLevel before allocating. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-06-18intel: Finalize the miptree before mapping it for fallbacks.Eric Anholt
Fixes segfault in mipmap_view.c demo. Bug #27212.
2010-06-18i965: Fix the name of aa_coverage_slope in the improved AA line params.Eric Anholt
2010-06-16intel: Remove unnecessary headers.Vinson Lee
2010-06-16r600: GL_COORD_REPLACE state is only relevant when point sprites are enabled.Henri Verbeet
2010-06-16r600: fix warningsMarc
2010-06-14i965: Remove unnecessary header.Vinson Lee
2010-06-14i965: Fix surface state dumping with INTEL_DEBUG=batch.Eric Anholt
I broke this with the state streaming changes.
2010-06-14i965: correct the gen6 line stipple enable define.Zhenyu Wang
2010-06-14intel: Remove long-dead comment about releasing texture heaps.Eric Anholt
BOs are stored in the bufmgr, which is freed as part of the screen structure.
2010-06-12i965: Fix gen6 front cull mode.Eric Anholt
2010-06-12i965: Use the new message header format for FF_SYNC on gen6.Zhenyu Wang
2010-06-12i965: Add support for math instructions in the gen6 WM.Zhenyu Wang
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