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Call the get_src_reg_imm() function when it's permissible to generate a
literal value src register.
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The value was always 1.
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1) Don't error-check here. It's done in glx makeCurrent.
2) Allow ctx and the dri drawables to be NULL for future use. This is
currently blocked in glx makeCurrent.
3) Avoid updating dri drawables unless they are completely uninitialized.
Since the updating was done outside of the lock, the driver need to
verify and redo it anyway.
Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
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Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
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This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.
This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
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Context destruction was nearly the same over all the drivers,
so collapse it down.
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This might trip up some serious FBO users, will have to see, but
it avoids the slow paths for all the demos I have.
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this fixes qtdemo-qt4 starting and a leak in glxgears exit
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This is because the DDX always allocates using the drawable sizes.
which gives me twice the depth buffer I asked for, dumb.
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We don't upload the pixels with the CPU in that case, so the map will
only serve as a way of triggering cache flushes over a bunch of data we
don't touch.
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i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8.
Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now.
While here, also add true srgb luminance / luminance_alpha support -
unfortunately the published docs fail to mention which asics support
this, tested on g43 so assume this works on any g4x.
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use color format constants instead of magic numbers
remove handling of cpp 0 or 3 (neither is possible) in various places
don't misconfigure 8 bit surface blits as rgb565
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if you hit this you've already failed but we shouldn't crash
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- remove disabled code
- silence compiler warnings (uinitialized values)
- remove unneeded code
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Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
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Fixes Sun cc error:
"r300_cmdbuf.c", line 142: invalid cast expression
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
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Since core Mesa MAX_TEXTURE_LEVELS was bumped, we were incorrectly advertising
a maximum texture size of 4096 on older chips, causing corrupted menu text in
Extreme Tux Racer or Armagetron.
Also make sure our texture image array can actually hold all the mipmap levels
we support...
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The FBO pixel coordinate system, with (0,0) as the
upper-left pixel, is inverted in Y compared to the
normal OpenGL pixel coordinate system, which has
(0,0) as its lower-left pixel.
Viewport and polygon stipple are sensitive to this
inversion; so is point rasterization. The basic
fix is simple: when rendering to an FBO, instead
of the normal RASTRULE_UPPER_RIGHT that's
appropriate for OpenGL windows, use the Y inversion
RASTRULE_LOWER_RIGHT.
Unfortunately, current Intel documentation has this
value listed as "Reserved, but not seen as useful".
It does work on at least some i965-class devices,
though; and the worst that could happen if an
older device didn't support it would be incorrect
point rasterization to FBOs, which is what happens
already, so this fix is at least no worse than what
happens presently, and is better for some (and possibly
all) i965-class devices.
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This also cuts instructions by just using the existing bit in the payload
rather than computing it from the determinant in the SF unit and passing it
as a varying down to the WM. Something still goes wrong with getting the
backface color right, but a simpler shader appears to get the right result.
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Previously, we would sample (f,glFrontFacing,undef,undef) instead of the
(f,0,0,1) that fragment.fogcoord is supposed to return. Due to
glFrontFacing's presence in FOGC.y, we'll still give bad results there when
glFrontFacing is used.
Bug #19122, piglit testcase fp-fog.
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