| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-11-16 | [intel] Add 965 support to shared intel_blit.c | Eric Anholt | |
| This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine. | |||
| 2007-11-16 | [i915] Pass static region names in so debugging says more than "static region". | Eric Anholt | |
| 2007-11-16 | [intel] Move additional code to be shared from intel_context.h to intel/. | Eric Anholt | |
| 2007-11-16 | [intel] Move intel_tex.h into place, forgotten in the previous commit. | Eric Anholt | |
| 2007-11-16 | [965] Add batchbuffer decode for several more packets. | Eric Anholt | |
| 2007-11-16 | [intel] Fix typos in intel_chipset.h macros. | Eric Anholt | |
| 2007-11-16 | [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them. | Eric Anholt | |
| 2007-11-16 | [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat. | Eric Anholt | |
| 2007-11-16 | [intel] Add some doxygen notes on what the bufmgr_fake block members mean. | Eric Anholt | |
| 2007-11-16 | [intel] Add a simple relocation cache to the fake buffer manager. | Eric Anholt | |
| This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them. | |||
| 2007-11-16 | [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c. | Eric Anholt | |
| They shouldn't be created, and this often helps catch stupid issues. | |||
| 2007-11-16 | [intel] Add support for multiple levels of relocation in bufmgr_fake. | Eric Anholt | |
| This is required for 965 support, which has relocations in other places than just the batchbuffer. | |||
| 2007-11-16 | [i915] Push locking in intelClearWithTris down inside meta_draw_poly. | Eric Anholt | |
| The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad. | |||
| 2007-11-15 | fix bogus assumption if ddx has set up surface reg for z buffer | Roland Scheidegger | |
| this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips. | |||
| 2007-11-12 | i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730 | Xiang, Haihao | |
| 2007-11-09 | [i915] Remove old frontbuffer rotation hack. | Eric Anholt | |
| This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately. | |||
| 2007-11-09 | [intel] By default, output batchbuffer decode to stderr like other debug info. | Eric Anholt | |
| 2007-11-09 | [intel] Initialize a depth buffer if the visual has depth 24 but no stencil. | Eric Anholt | |
| 2007-11-09 | [intel] Move over files that will be shared with 965-fbo work. | Eric Anholt | |
| 2007-11-09 | code clean-ups, reformatting | Benno Schulenberg | |
| 2007-11-09 | recreate from changed gl_API.xml | Roland Scheidegger | |
| 2007-11-08 | fix Unichrome/Blender crash, bug 13142 | Benno Schulenberg | |
| 2007-11-06 | r200: Re-expose SetTexOffset functionality. | Michel Dänzer | |
| This seems to have been mismerged with the DRI interface changes. | |||
| 2007-11-06 | r200: Fix SetTexOffset format for 16 bit pixmaps/textures. | Michel Dänzer | |
| Use symbolic array indices to clarify. | |||
| 2007-11-05 | Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL. | Oliver McFadden | |
| 2007-11-05 | r300: initial user clipping for TCL paths | Dave Airlie | |
| I've no idea if this code might break something or how it should interact with vertex shaders, it makes the clip demo work for me | |||
| 2007-11-03 | r300: move more vap registers out of non tcl paths | Dave Airlie | |
| 2007-11-03 | r300: fix misnumber register | Dave Airlie | |
| 2007-11-03 | r300: fix texwrap border color | Dave Airlie | |
| 2007-11-01 | nouveau: ppc, swap fragment programs on big endian systems. | Dave Airlie | |
| Thanks to the PS3 RSX project for figuring this out. | |||
| 2007-11-01 | i915: make i915 use the cached mappings for batch/buffer objects. | Dave Airlie | |
| This should restore gears speed on 9xx hardware | |||
| 2007-10-30 | Alias glStencilOpSeparateATI with glStencilOpSeparate. | Brian | |
| 2007-10-30 | Finish up ATI_separate_stencil | Brian | |
| Add entrypoints to glapi XML file and regenerate files. Implement glStencilOpSeparateATI(). Consolidate some code in stencil.c | |||
| 2007-10-30 | More vblank cleanups. | Michel Dänzer | |
| * Fix crash at context creation in most drivers supporting vblank. * Don't pass vblank sequence or flags to functions that get passed the drawable private already. * Attempt to initialize vblank related drawable private fields just once per drawable. May need more work in some drivers. | |||
| 2007-10-29 | [i915] Include header to pick up intel_ttm_bo_create_from_handle() proto. | Eric Anholt | |
| 2007-10-29 | Merge branch 'origin' | Eric Anholt | |
| 2007-10-29 | Refactor and fix core vblank support | Jesse Barnes | |
| Consolidate support for synchronizing to and retrieving vblank counters. Also fix the core vblank code to return monotonic MSC counters, which are required by some GLX extensions. Adding support for multiple pipes to a low level driver is fairly easy, the Intel 965 driver provides simple example code (see intel_buffers.c:intelWindowMoved()). The new code bumps the media stream counter extension version to 2 and adds a new getDrawableMSC callback. This callback takes a drawablePrivate pointer, which is used to calculate the MSC value seen by clients based on the actual vblank counter(s) returned from the kernel. The new drawable private fields are as follows: - vblSeq - used for tracking vblank counts for buffer swapping - vblFlags - flags (e.g. current pipe), updated by low level driver - msc_base - MSC counter from the last time the current pipe changed - vblank_base - kernel DRM vblank counter from the last time the pipe changed Using the above variables, the core vblank code (in vblank.c) can calculate a monotonic MSC value. The low level DRI drivers are responsible for updating the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags) along with msc_base and vblank_base whenever the pipe associated with a given drawable changes (again, see intelWindowMoved for an example of this). Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to driDrawableGetMSC32 and add code for pipe switching as outlined above to fully support the new scheme. | |||
| 2007-10-26 | Merge branch '965-glsl' | Zou Nan hai | |
| Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c | |||
| 2007-10-18 | i915: Add some sanity checks to blit command debugging code. | Michel Dänzer | |
| 2007-10-17 | Framework for supporting z24_s8 and z32 depth textures on r300. | Ian Romanick | |
| 2007-10-17 | Initial support for ARB_depth_texture | Ian Romanick | |
| Currently only GL_DEPTH_COMPONENT16 are supported. I don't know what the hardware bits are to select the other formats, but it shouldn't be too hard to figure out. | |||
| 2007-10-17 | mga: Enable (trivial) support for GL_APPLE_vertex_array_object, bump DRIVER_DATE | Ian Romanick | |
| 2007-10-17 | mga: Enable (trivial) support for GL_EXT_gpu_program_parameters. | Ian Romanick | |
| 2007-10-17 | i915: Don't emit 'empty' blit rectangles. | Michel Dänzer | |
| The hardware seems to interpret them differently and produce unexpected results... | |||
| 2007-10-16 | Replace symlink generation from i915 with files in intel/ and symlinks there. | Eric Anholt | |
| 2007-10-16 | i915: Make sure extensions that require TTM actually work. | Michel Dänzer | |
| 2007-10-16 | i915: fixup TTM interfaces to follow drm changes | Dave Airlie | |
| 2007-10-16 | i915: Re-enable __DRItexOffsetExtension. | Michel Dänzer | |
| This seems to have got lost somehow during the recent DRI interface changes. | |||
| 2007-10-12 | Merge branch 'dri2' | Kristian Høgsberg | |
| Conflicts: src/mesa/drivers/dri/i915/intel_screen.c | |||
| 2007-10-12 | Merge branch 'master' into i915-superioctl | Dave Airlie | |
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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