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path: root/src/mesa/drivers/dri
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2008-02-14[i965] gl_FrontFacing supportZou Nan hai
2008-02-14i965: remove unused hal hooksDave Airlie
These don't appear to have ever been used.
2008-02-13[965] Fix ARB_occlusion_query from intel_screen.c merge.Eric Anholt
It wasn't being initialized at screen setup, so we were getting stub entrypoints even though it was exposed as enabled. Fixes arbocclude mesa demo.
2008-02-13[intel] Fix 965 rendering with non-TTM by merging intel_ioctl between 915/965.Eric Anholt
The 965 path wasn't setting pClipRects for batch submission since it didn't want kernel cliprect handling before. The 915 path also grew the INTEL_NO_HW=1 option for testing just driver overhead.
2008-02-13When mapping, wait on the buffer's fence, not hardware idle, in bufmgr_fakeEric Anholt
2008-02-13Remove O(n^2) debugging code from non-debug path of dri_bufmgr_fake.Eric Anholt
2008-02-12[intel] Remove cached reloc data buffer now that it's not a BO.Eric Anholt
It's not worth the extra effort to avoid a free/malloc, and we'd rather auto-size the reloc data buffer at some point so we don't need to have max_relocs.
2008-02-12[intel] Fix type of some more flags variables for uint64_t flags.Eric Anholt
Harmless since we don't yet have any bits above 31 for flags.
2008-02-12[intel] Note when BO map/unmap fail with TTM.Eric Anholt
2008-02-12[intel] Fix INTEL_DEBUG=bufmgr after relocation interface fixups.Eric Anholt
2008-02-12[965] Remove stale brw_state_cache.c comment and function export.Eric Anholt
2008-02-12nouveau: ddx versioning changedBen Skeggs
2008-02-07[965] Flush icache on new batch, not just new context.Eric Anholt
This is required since our buffer manager may now move our instruction-containing buffers at any batchbuffer emit.
2008-02-06[915] Fix COS function using same plan as SIN.Eric Anholt
The previous COS function failed badly outside of [-pi/2, pi/2].
2008-02-06[915] Use a quartic term to improve the accuracy of SIN results.Eric Anholt
This is described in the link in the comment, and is the same technique that r300 uses.
2008-02-06[915] Fix fp SIN function, and use a quadratic approximation instead of Taylor.Eric Anholt
The Taylor series notably fails at producing sin(pi) == 0, which leads to discontinuity every 2*pi. The quadratic gets us sin(pi) == 0 behavior, at the expense of going from 2.4% THD with working Taylor series to 3.8% THD (easily seen on comparative graphs of the two). However, our previous implementation was producing sin(pi) < -1 and worse, so any reasonable approximation is an improvement. This also fixes the repeating behavior, where the previous implementation would repeat sin(x) for x>pi as sin(x % pi) and the opposite for x < -pi.
2008-02-05[965] Bug 14314: assertion failure with with !AIGLX and depth=24 visual.Eric Anholt
2008-02-05[965] Fix TTM relocation caching overzealousness.Eric Anholt
The failure mode that was a available was: reloc 1 -> target_buf exec: PRESUMED_OFFSET wrong, buffer migrates, r1 entry updated. reloc 2 -> target_buf exec: suppose buffer migrates again. PRESUMED_OFFSET wrong. r2 entry updated. reloc 1 -> target_buf exec: suppose buffer doesn't migrate. PRESUMED_OFFSET right. no relocations performed. r1 has stale pointer at original location. Failures were reported with OGLconform's VBO test and SPECviewperf90, though I haven't confirmed that this fixes it.
2008-02-05i965: adjust the byte order of clear color. fix #14165Xiang, Haihao
2008-02-04Replace usage of DRM_BO_FLAG_MEM_TT in intel_regions.c with local/cached.Eric Anholt
In addition to potentially binding when it was about to be mapped anyway, failure to use CACHED_MAPPED means eating a full wbinvd on validate. Thanks to airlied for catching this.
2008-02-04[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.Eric Anholt
This helps us avoid a bunch of mess with gl_client_arrays that we filled with unused data and confused readers.
2008-02-04[965] Remove dead structure in brw_draw_upload.c.Eric Anholt
2008-02-04[965] Move temporary vbo array storage into the function using it.Eric Anholt
2008-02-04[965] Remove dead brw_vertex_element members.Eric Anholt
2008-02-04[965] Add a wrapper around interleaved copy_array_to_vbo_array for profiling.Eric Anholt
If compiled with optimization, it shouldn't appear at all, and helps me for now.
2008-02-04[965] Avoid overloaded use of the term 'input' for clarity.Eric Anholt
2008-02-04[965] Replace VEP/VBP state structures with inline batch emits.Eric Anholt
2008-02-04r300: fix isosurf on rs690Dave Airlie
2008-02-03i965: fix potential NULL pointer dereference. The third regionXiang, Haihao
isn't created at all for 965
2008-02-01[965] Fix indentation.Eric Anholt
2008-02-01Revert "intel: don't apply the relocation optimization if a target"Eric Anholt
This reverts commit e2cb905bc6e23eaafaeeb2abdc9480e70959ee3f. It was a reversion of an optimization hidden as otherwise. pre_target_buf_handle was always NULL, so the optimization was never enabled, rather than fixing the important optimization (resulting in 25-50% performance loss).
2008-02-01[965] Replace XXX comment about constant swizzle with an assert.Eric Anholt
2008-02-01[965] Fix some indentation in brw_vs_tnl.c.Eric Anholt
2008-02-01 [intel] fix for previous fixZou Nan hai
2008-02-01 [intel] use _mesa_copy_rect for upload compressed texture,Zou Nan hai
this fix bad texture issue in some games(UT and quake).
2008-02-01i965: Don't emit state if fall back to software rendering. fix #14116Xiang, Haihao
2008-01-31[i965] renable regative rhw testZou Nan hai
2008-01-31intel: don't apply the relocation optimization if a targetXiang, Haihao
buffer is used for a relocatee in the former relocation process then another target buffer is used for this relocatee at the same offset in the current relocation process.
2008-01-29Add new RV380 pci idAlex Deucher
bug 14289
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-27r300: add initial rs690 support to MesaDave Airlie
The rs690 has an rs4xx style vertex-shader less 3D engine. It uses the new r500 output engine though. It also needs a new drm with rs690 support, which is just getting cleaned up.
2008-01-25i965: valid message length includes message header.Xiang, Haihao
2008-01-25i965: re-define the type of reg.loopcount.Xiang, Haihao
avoid some issues such that 1 + (-2) gets a big positive value.
2008-01-24Bufmgr cleanup from intel-batchbuffer branch of 2d driver.Eric Anholt
2008-01-24Clean up comments/dead code from relocation buffer change.Eric Anholt
2008-01-24i915: move to using copy from user for relocationsDave Airlie
2008-01-22[intel] Clean up references to screen buffer metrics.Kristian Høgsberg
The screen wide info such as pitch and cpp are obsoleted by the FBO changes, so clean up the last few references to those, except for setting up the legacy screen regions.
2008-01-19[965] Fix WM unit cache keying that broke line stipple and polygon offset.Eric Anholt
2008-01-18[intel] Fix memory leak with fake bufmgr.Eric Anholt
2008-01-18[965] Do a little bit rotation in state hash to reduce collisions.Eric Anholt
This was around 3% improvement in OA.