| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-06-12 | Merge master and fix conflicts | Alex Deucher | |
| 2009-06-12 | radeon: fix size of mipmap texture array | Dave Airlie | |
| 2009-06-12 | radeon/r200/r300: fix max texture levels assert | Dave Airlie | |
| use the actual value set in the context | |||
| 2009-06-12 | Merge remote branch 'main/radeon-rewrite' | Dave Airlie | |
| 2009-06-11 | Add RV740 support | Alex Deucher | |
| 2009-06-11 | r300: fix VAP setup | Maciej Cencora | |
| If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang. | |||
| 2009-06-11 | r300: fix for SW TCL path | Maciej Cencora | |
| We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8. | |||
| 2009-06-11 | r300: don't send unused attributes for SW TCL path | Maciej Cencora | |
| 2009-06-11 | r300: send only RS_IP_* regs that we are going to use | Maciej Cencora | |
| 2009-06-11 | r300: fix RS setup when no colors and textures are sent to FP | Maciej Cencora | |
| RS_COL_FMT field is part of RS_IP_* reg not RS_INST_* | |||
| 2009-06-11 | r300: r500 fragment program fixes | Maciej Cencora | |
| - when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory | |||
| 2009-06-11 | radeon: increase max bo count | Maciej Cencora | |
| 2009-06-11 | r300: fix a GPU lock up | Maciej Cencora | |
| Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK. | |||
| 2009-06-11 | r300: fix vertex program bug | Maciej Cencora | |
| If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests. | |||
| 2009-06-11 | r300: move some code for easier debugging | Maciej Cencora | |
| 2009-06-11 | r300: print vertex program when debugging is enabled | Maciej Cencora | |
| 2009-06-11 | r300: fix output register allocation for vertex shaders | Maciej Cencora | |
| If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases. | |||
| 2009-06-11 | r300: hw doesn't support saturation for tex instructions | Maciej Cencora | |
| 2009-06-11 | r300: fix indexed primitive rendering when using memory manager | Jerome Glisse | |
| 2009-06-11 | Properly set aos_count | Alex Deucher | |
| This is used by radeonReleaseArrays to free AOS. | |||
| 2009-06-11 | intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL. | Michel Dänzer | |
| Fixes glean depthStencil test. | |||
| 2009-06-10 | move radeon_set_screen_flags() up so CHIP_FAMILY is set before using it | Alex Deucher | |
| fixes last commit. | |||
| 2009-06-10 | Use correct scratch reg offset for r6xx/r7xx | Alex Deucher | |
| 2009-06-10 | r300: make sure indexed rendering doesn't try to use more than the num of ↵ | Jerome Glisse | |
| vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer. | |||
| 2009-06-09 | Pull in additional state setup from the DDX | Alex Deucher | |
| 2009-06-09 | i915: Add an option for testing the effect of early Z in classic mode. | Eric Anholt | |
| The early Z stuff is supposed to be unsafe without some more work in the enable/disable path (in particular, how do we want to get it disabled on the way out to the X Server?), but at the moment is 6% in OA. | |||
| 2009-06-09 | intel: Remove an unneeded hunk that slipped in with texture tiling. | Eric Anholt | |
| intel_miptree_pitch_align does this later on. | |||
| 2009-06-09 | intel: Base tri clearing depth on Y tiling, not IS_I965(). | Eric Anholt | |
| Y tiling is why the 965 check was there, but I wanted to experiment with Y on pre-965 as well. | |||
| 2009-06-09 | intel: Fix intel_region_unmap to do unmap, not map. | Eric Anholt | |
| Thanks to Shuang He for catching this. | |||
| 2009-06-09 | i965: added intelFlush() call in intel_get_tex_image() | Brian Paul | |
| Fixes the render-to-texture test in progs/tests/getteximage.c | |||
| 2009-06-09 | intel: use GLboolean, not int, for compressed parameter | Brian Paul | |
| 2009-06-09 | intel: make a bunch of glTexImage-related functions static | Brian Paul | |
| 2009-06-09 | intel: whitespace clean-ups | Brian Paul | |
| 2009-06-09 | intel: remove extra \n from warning string | Brian Paul | |
| 2009-06-09 | radeon: fix mipmap_limits crasher. | Dave Airlie | |
| This gets the correct srclvl image map when uploading images to the new mipmap. | |||
| 2009-06-08 | r300: fix regression caused by 056bc77547c304021a0faf204897ed238a5cf424 | Maciej Cencora | |
| Fixes GPU hangs in software TCL path | |||
| 2009-06-07 | Merge remote branch 'origin/master' into radeon-rewrite | Dave Airlie | |
| 2009-06-07 | r300: Endianness fixes for recent vertex path changes. | Michel Dänzer | |
| Signed-off-by: Maciej Cencora <m.cencora@gmail.com> | |||
| 2009-06-07 | r300: vertex array stride = 0 means that data are tightly packed in the array | Maciej Cencora | |
| 2009-06-07 | r300: GL_(U)SHORT and GL_(U)BYTE with < 4 components can also be HW accelerated | Maciej Cencora | |
| Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT. Fix license header too. Reported by: Nicolai Hähnle <nhaehnle@gmail.com> | |||
| 2009-06-07 | r300: remove unused code | Maciej Cencora | |
| 2009-06-07 | r300: rewrite vertex setup for software T&L path using functions from ↵ | Maciej Cencora | |
| software TCL path | |||
| 2009-06-07 | r300: prepare for some code duplication removal | Maciej Cencora | |
| 2009-06-07 | r300: enable EXT_vertex_array_bgra extensions | Maciej Cencora | |
| 2009-06-07 | r300: add hw accelerated support for different vertex data formats | Maciej Cencora | |
| 2009-06-07 | r300: prepare for different vertex data type support | Maciej Cencora | |
| 2009-06-07 | r300: fixup vertex attributes ordering | Maciej Cencora | |
| Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays. | |||
| 2009-06-07 | r300: always pass 4 color components to RS unit | Maciej Cencora | |
| Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components. | |||
| 2009-06-04 | re-arrange state structure | Alex Deucher | |
| - split out renderbuffers - split out shaders - split our viewports Only send the state needed. | |||
| 2009-06-04 | Don't program VGT_OUT_DEALLOC_CNTL/VGT_VERTEX_REUSE_BLOCK_CNTL | Alex Deucher | |
| These are chip specific and are programmed by the drm. This should fix hangs on some chips. | |||
 |
index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
| summaryrefslogtreecommitdiff |