Age | Commit message (Collapse) | Author |
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These regs don't use the SET_CONTEXT_REG packet,
so they weren't getting set correctly.
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make sure we allocate enough space for relocs
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This fixes problem that dma buffers were leaking in dri1 mode.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
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Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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This fixes problems when application is using large vertex arrays for drawing.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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In radeonRefillCurrentDmaRegion() make sure we
unmap the previous buffer.
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Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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This allows us to return the unused portion of the dma buffer
to the allocator instead of wasting nearly 16k a pop.
Cherry picked and ported to new code by Pauli.
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Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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make sure the number of indices is valid for the
requested prim type. glxgears sends invalid
quad strips with only 2 indices for example.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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Split vbo rendering when the number of elements requested
by drawarrays is bigger than 65536.
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Supported only on HW with TCL block and with proper radeon drm.
Required minimum radeon drm version is 1.30 or KMS.
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TODO:
- use proper interface for checking if bo is idle when it's available
- disable ZTOP only when needed
- make it work under KMS
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Hopefully this gets the ordering correct so the space checks don't fail.
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Based on Maciej's code, just fixed up the alignments for INDX_BUFFER
ut2004 runs AS-Convoy
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if stride is 0 we cannot use count as max index for bounds checking,
since the hardware will simply return 0 as data for indices failing
bounds check. If stride is 0 any index should be valid hence simply
disable bounds checking in this case.
This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
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Conflicts:
src/mesa/drivers/dri/r300/r300_draw.c
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Revert to previous behaviour of dropping to big render operations.
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Copy elements directly to DMA bo to get rid of one memcpy, and prepare for using VBOs for index buffer.
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This doesn't remove software TCL path - so RS480 and RS690 work as before.
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Using drm_i915_sarea_t instead of struct drm_i915_sarea seems to be
a common standard now, therefore fix it also in intel_context
structure. Additionally this silences a compiler warning:
intel_swapbuffers.c: In function `intelFixupVblank':
intel_swapbuffers.c:48: warning: initialization from incompatible pointer type
Signed-off-by: Tobias Doerffel <tobias.doerffel@gmail.com>
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Reported by adamk on #radeon
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