summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri
AgeCommit message (Collapse)Author
2008-07-09i915: fall back to software rendering when shadow comparison isXiang, Haihao
enabled for 1D texture. fix #12176
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-07-06Set library and header installation directories from configurationDan Nicholson
Currently the installation directories for libraries and headers are resolved within the install commands. For instance, the libraries will be installed to $(INSTALL_DIR)/$(LIB_DIR). This limits the flexibility of the installation, such as when the libraries should be installed to a subdirectory like /usr/lib/tls. This adds the make variables $(INSTALL_LIB_DIR) and $(INSTALL_INC_DIR) to define the locations that the libraries and headers are installed. For the static configs, this resolves exactly as before to $(INSTALL_DIR)/include and $(INSTALL_DIR)/$(LIB_DIR). For autoconf, they are derived directly from the --libdir and --includedir settings.
2008-07-06r500_fragprog: Fix RSQ with negative parametersNicolai Haehnle
2008-07-06r300_fragprog: Emulate trigonometric functions in radeon_program_aluNicolai Haehnle
2008-07-06r300: Translate fragment program DST in radeon_program_aluNicolai Haehnle
2008-07-06r300: Translate fragment program LRP in radeon_program_alu.cNicolai Haehnle
2008-07-06r300: Allow adding parameters during fragprog transform, share LIT codeNicolai Haehnle
2008-07-05r300: Correctly scan for used temporary registersNicolai Haehnle
This fixes a regression introduced by dea8719f0...
2008-07-05r500: Major refactoring of fragment program emitNicolai Haehnle
Use the common facilities to convert non-native instructions into native ones. Worked hard to make the code easier to read (hopefully), by using helper functions instead of direct manipulation of the machine code. Fixes two bugs related to FLR and XPD.
2008-07-05r300: Remove clause stuff for now in favour of a cloned generic gl_programNicolai Haehnle
2008-07-05r500_fragprog: Cleanup some unused variables and code.Nicolai Haehnle
2008-07-05r500: Fix a mixup in fragment program LRP instruction emitNicolai Haehnle
2008-07-05r500: Fix blend color.Nicolai Haehnle
2008-07-04r300: Fix depth texture in compare modeNicolai Haehnle
Missed the homogenous divide of R by Q before...
2008-07-02intel: span rendering requires just a flush before starting, not finish.Eric Anholt
The dri_bo_map()s that follow will take care of idling the hardware as needed.
2008-07-02mesa: fix issues around multisample enableRoland Scheidegger
multisample enable is enabled by default, however gl mandates multisample rendering rules only apply if there's also a multisampled buffer.
2008-07-02intel-gem: Emit an MI_FLUSH at glFlush() so frontbuffer rendering is flushed.Eric Anholt
We have something similar in the X Server that covers X Server rendering, this is the equivalent here for rendering to the front buffer. If we cared about avoiding this at glFlush time, we could only do this when some actual frontbuffer rendering had occurred. Bug #16392.
2008-07-02intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
2008-07-02intel-gem: Fix Y-tiling span setup.Eric Anholt
The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
2008-07-02set ctx->Const.MaxVertexTextureImageUnits = 0Brian Paul
This disallows vertex shader texture sampling. See bugs 16157, 13838.
2008-07-02VBO: Regenerate files based on recent changes to gl_API.xmlIan Romanick
Since GL_ARB_vertex_buffer_object protocol isn't supported yet, these changes are innocuous.
2008-07-01intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt
It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
2008-07-01dri: drop asserts to make build against stable libdrmDave Airlie
These asserts are of questionable use at the moment with things in flux.
2008-07-01dri: Take the base image size into account when computingXiang, Haihao
first level of the mipmap. fix #16210
2008-06-30r3xx/r5xx: Enable ARB_point_parameters.Corbin Simpson
This isn't complete yet. It does cover the two most common usage cases, though, and at least the third one (POINT_DISTANCE_ATTENUATION) is possible, so I'll do that later.
2008-06-30r300: Fix dumb mistake in LOD bias translationNicolai Haehnle
2008-06-30r300: Cleanup LodBias supportNicolai Haehnle
. There is both a per-texture unit and a per-texture object (at least for OpenGL 1.4); this should now be supported properly. . The LOD bias calculation in r300_state has been simplified and corrected (need to multiply by 32 instead of 31, and ensure clamping) . do not clamp LOD bias in TexEnv, as that behaviour conflicts with what the spec says . set Const.MaxTextureLodBias properly . remove the no_neg_lod_bias property; if somebody can explain what it's good for, we can add it back in, but according to Google, nobody seems to use it . removed some dead code and unused variables
2008-06-29r300: Change LOD bias emission to more closely follow per-tex rules.Corbin Simpson
Okay, this time it's for real, and for good. This should be a perma-fix.
2008-06-29r300: Fix wrap mode for 1D texturesNicolai Haehnle
2008-06-27DRI-specific pkg-config fileDan Nicholson
Since the gl pkg-config file doesn't convey any specifics about the backend in use, this adds a new pkg-config file for when DRI is in use. This can be used by the xserver build to determine if the DRI and/or GLX extensions are appropriate.
2008-06-26intel: Fix locking when doing intel_region_cow().Eric Anholt
This was broken in the merge of 965 blit support. It tried to lock only when things were already locked.
2008-06-26intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt
Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
2008-06-26Check in SwapBuffers for any new pending dri2 eventsAlan Hourihane
2008-06-24Merge commit 'origin/master' into drm-gemEric Anholt
2008-06-24intel: Fix glCopyPixels when x or y are < 0 in hw coordinates.Eric Anholt
Nothing would get drawn as the negative coordinates broke the rectangle intersection code that used unsigned ints. Tested with copypix demo and sliding the copy to the upper left.
2008-06-24i965: Use the shared intel_pixel_copy.c.Eric Anholt
This disables the textured copy implementation on 965, which didn't appear to work (mesa copypix demo, disable the blit path, move so that regions don't overlap and textured is used, and you get garbage). If we resurrect this for i965, I'd rather it used the 915-style metaops instead. Current metaops code left in place so that whoever picks it up has a reference.
2008-06-24intel: Same pixel function init for everyone now.Eric Anholt
2008-06-24intel: Avoid glBitmap software fallback for blending when no blending occurs.Eric Anholt
Mesa demos tend to leave blending on but in GL_ONE/GL_ZERO, or GL_SRC_ALPHA/GL_ONE_MINUS_SRC_ALPHA with a source alpha of 1.0.
2008-06-24intel: Merge check_blit_fragment_ops between i915/i965.Eric Anholt
Both had some useful bits for the other.
2008-06-24intel: Note reasons for blit pixel op fallbacks under INTEL_DEBUG=pix.Eric Anholt
2008-06-24i915: Add support for accelerated glBitmap, shared from 965.Eric Anholt
2008-06-24i915: Fix read != draw drawable for glCopyPixels.Eric Anholt
Taken from commit bad6e175cf59cce630c37d73f6e71f3a4de50ae6.
2008-06-24i915: Allow accelerated pixel ops to be disabled with INTEL_NO_BLIT.Eric Anholt
This matches 965.
2008-06-23i915: Accumulate the VB into a local buffer and subdata it in.Eric Anholt
This lets GEM use pwrite, for an additional 4% or so speedup.
2008-06-23i915: Convert to using VBs instead of inline prims.Eric Anholt
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul