Age | Commit message (Collapse) | Author | |
---|---|---|---|
2009-11-13 | i965: Remove an unused cache_item field. | Eric Anholt | |
2009-11-13 | i965: Remove long dead structures for ffvertex_prog.c. | Eric Anholt | |
2009-11-13 | i965: Use bo_map instead of subdata to upload the bits of constant buffer. | Eric Anholt | |
Saves CPU time, resulting in a 2.5% FPS win on ETQW. | |||
2009-11-13 | i965: Validate the number of URB entries selected for the VS. | Eric Anholt | |
2009-11-13 | intel: When subdataing a busy buffer, use a temporary and blit in. | Eric Anholt | |
This cuts a massive number of waits in ET:QW, which uses a VBO ringbuffer. Unfortunately it doesn't BufferData when wrapping back to 0, so we can't be clever with tracking what's been initialized. | |||
2009-11-13 | i965: Clean up Ironlake sampler type definitions. | Eric Anholt | |
They're the same regardless of execution width for 8, 4x2, and 16. | |||
2009-11-13 | i965: Avoid moving the current value back into the accumulator for MAD. | Eric Anholt | |
This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms. | |||
2009-11-12 | intel: Don't check for context pointer to be NULL during extension init | Ian Romanick | |
Thanks to Chia-I Wu's changes to the extension function infrastructure, we no longer have to tell the loader which extensions the driver might enable. This means that intelInitExtensions will never be called with a NULL context pointer. Remove all the NULL checks. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> | |||
2009-11-12 | intel: Remove unused enable_imaging parameter to intelInitExtensions | Ian Romanick | |
2009-11-11 | r300, r300g: Add missing registers. | Corbin Simpson | |
2009-11-10 | Merge remote branch 'origin/mesa_7_6_branch' | Eric Anholt | |
2009-11-10 | i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile. | Eric Anholt | |
For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase). | |||
2009-11-10 | i965: Add a note explaining the data cache domain. | Eric Anholt | |
2009-11-10 | i965: Fix VS constant buffer value loading. | Eric Anholt | |
Previously, we'd load linearly from ParameterValues[0] for the constants, though ParameterValues[1] may not equal ParameterValues[0] + 4. Additionally, the STATE_VAL type paramters didn't get updated. Fixes piglit vp-constant-array-huge.vpfp and ET:QW object locations. Bug #23226. | |||
2009-11-10 | i965: Unalias src/dst registers for SGE and friends. | Eric Anholt | |
Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 (cherry picked from commit 56ab92bad8f1d05bc22b8a8471d5aeb663f220de) | |||
2009-11-10 | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp. | Eric Anholt | |
Fixes piglit arl.vp. (cherry picked from commit d52d78b4bcd6d4c0578f972c0b8ebac09e632196) | |||
2009-11-10 | i965: Unalias src/dst registers for SGE and friends. | Eric Anholt | |
Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 | |||
2009-11-10 | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp. | Eric Anholt | |
Fixes piglit arl.vp. | |||
2009-11-09 | r600/r700: typo, fix mask of DB_ALPHA_TO_MASK | Jerome Glisse | |
2009-11-09 | r600: don't emit htile regs | Alex Deucher | |
These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm. | |||
2009-11-09 | r600: rework DB render setup | Alex Deucher | |
- consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z | |||
2009-11-09 | r600: don't emit htile regs | Alex Deucher | |
These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm. | |||
2009-11-09 | r600: add missing ZPASS setup bits for r7xx+ | Alex Deucher | |
2009-11-06 | i965: Use Compr4 instruction compression mode on G4X and newer. | Eric Anholt | |
No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size. | |||
2009-11-06 | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
2009-11-06 | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
This should fix issues with antialiased lines in GLSL. | |||
2009-11-06 | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst. | |||
2009-11-06 | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
2009-11-06 | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
2009-11-06 | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
2009-11-06 | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
2009-11-06 | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. | Eric Anholt | |
2009-11-06 | i965: Use a normal alu1 emit for OPCODE_TRUNC. | Eric Anholt | |
2009-11-06 | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c | Eric Anholt | |
This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain. | |||
2009-11-06 | i965: Collect GLSL src/dst regs up in generic code. | Eric Anholt | |
This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced. | |||
2009-11-06 | intel: better front color buffer test in intelClear() | Brian Paul | |
2009-11-06 | i965: Always pass the size argument to brw_cache_data. | Eric Anholt | |
This keeps the individual state files from having to export their structures for brw_state_cache initialization. | |||
2009-11-06 | intel: Finish removing the fallback code for bug #16697. | Eric Anholt | |
I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54. | |||
2009-11-06 | intel: Don't validate in a texture image used as a render target. | Eric Anholt | |
Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation. | |||
2009-11-06 | intel: Clean up some extra struct indirection in finalize. | Eric Anholt | |
2009-11-06 | intel: Use _mesa_get_current_tex_object() to clean up TFP path. | Eric Anholt | |
2009-11-06 | intel: Remove duplicated arguments from intel_miptree_match_image(). | Eric Anholt | |
2009-11-06 | i965: Remove an XXX comment for testing some code that seems to work. | Eric Anholt | |
2009-11-06 | intel: Remove obsolete comment about GEM in the spans code. | Eric Anholt | |
2009-11-06 | intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing. | Eric Anholt | |
This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary. | |||
2009-11-06 | Make a convenient int for what chipset generation we're on. | Eric Anholt | |
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks. | |||
2009-11-06 | intel: call intel_check_front_buffer_rendering() in intelClear() | Brian Paul | |
fixes bug 24953. | |||
2009-11-04 | r600: rework draw functions | Alex Deucher | |
Seems INDX_OFFSET doesn't work properly on some cards, so change back to immediate mode indices. Seems to only affect DRI1. Needs more investigation. Rework and clean up the draw functions. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
2009-11-04 | r600: fix count prediction for IB case | Alex Deucher | |
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
2009-11-04 | Fix YTILE spantmp functions | Alan Hourihane | |