| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-10-08 | i965: Add register coalescing to the new FS backend. | Eric Anholt | |
| Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by eliminating the moves used in ir_assignment and ir_swizzle handling. Still 16.5% to go to catch up to the Mesa IR backend, presumably because instructions are almost perfectly mis-scheduled now. | |||
| 2010-10-08 | i965: Enable attribute swizzling (repositioning) in the gen6 SF. | Eric Anholt | |
| We were trying to remap a fully-filled array down to only handing the WM the components it uses. This is called attribute swizzling, and if you don't enable it you just get 1:1 mappings of inputs to outputs. This almost fixes glsl-routing, except for the highest gl_TexCoord[] indices. | |||
| 2010-10-08 | i965: Fix new FS gen6 interpolation for sparsely-populated arrays. | Eric Anholt | |
| We'd overwrite the same element twice. | |||
| 2010-10-08 | i965: Fix gen6 WM push constants updates. | Eric Anholt | |
| We would compute a new buffer, but never point the hardware at the new buffer. This partially fixes glsl-routing, as now it get the updated uniform for which attribute to draw. | |||
| 2010-10-08 | i965: Handle swizzles in the addition of YUV texture constants. | Eric Anholt | |
| If someone happened to land a set in a different swizzle order, we would have assertion failed. | |||
| 2010-10-08 | i965: Drop the check for YUV constants in the param list. | Eric Anholt | |
| _mesa_add_unnamed_constant() already does that. | |||
| 2010-10-08 | i965: Drop the check for duplicate _mesa_add_state_reference. | Eric Anholt | |
| _mesa_add_state_reference does that check for us anyway. | |||
| 2010-10-07 | i965: Normalize cubemap coordinates like is done in the Mesa IR path. | Eric Anholt | |
| Fixes glsl-fs-texturecube-2-* | |||
| 2010-10-07 | i965: Disable emitting if () statements on gen6 until we really fix them. | Eric Anholt | |
| 2010-10-07 | gles2: Add GL_EXT_texture_format_BGRA8888 support | Kristian Høgsberg | |
| 2010-10-06 | i965: Fix gen6 pointsize handling to match pre-gen6. | Eric Anholt | |
| Fixes point-line-no-cull. Bug #30532 | |||
| 2010-10-06 | i965: Don't assume that WPOS is always provided on gen6 in the new FS. | Eric Anholt | |
| We sensibly only provide it if the FS asks for it. We could actually skip WPOS unless the FS needed WPOS.zw, but that's something for later. Fixes: glsl-texture2d and probably many others. | |||
| 2010-10-06 | i965: Add support for gl_FrontFacing on gen6. | Eric Anholt | |
| Fixes glsl1-gl_FrontFacing var (2) with new FS. | |||
| 2010-10-06 | i965: Refactor gl_FrontFacing setup out of general variable setup. | Eric Anholt | |
| 2010-10-06 | i965: Gen6's sampler messages are the same as Ironlake. | Eric Anholt | |
| This should fix texturing in the new FS backend. | |||
| 2010-10-06 | i965: Don't do 1/w multiplication in new FS for gen6 | Eric Anholt | |
| Not needed now that we're doing barycentric. | |||
| 2010-10-06 | i965: Add some clarification of the WECtrl field. | Eric Anholt | |
| 2010-10-06 | i965: Fix botch in the header_present case in the new FS. | Eric Anholt | |
| I only set it on the color_regions == 0 case, missing the important case, causing GPU hangs on pre-gen6. | |||
| 2010-10-06 | i965: Fix up IF/ELSE/ENDIF for gen6. | Eric Anholt | |
| The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet). | |||
| 2010-10-06 | i965: Gen6 no longer has the IFF instruction; always use IF. | Eric Anholt | |
| 2010-10-06 | i965: Add back gen6 headerless FB writes to the new FS backend. | Eric Anholt | |
| It's not that hard to detect when we need the header. | |||
| 2010-10-06 | i965: Also do constant propagation for the second operand of CMP. | Eric Anholt | |
| We could do the first operand as well by flipping the comparison, but this covered several CMPs in code I was looking at. | |||
| 2010-10-06 | i965: Enable the constant propagation code. | Eric Anholt | |
| A debug disable had slipped in. | |||
| 2010-10-04 | i965: Add support for gen6 FB writes to the new FS. | Eric Anholt | |
| This uses message headers for now, since we'll need it for MRT. We can cut out the header later. | |||
| 2010-10-04 | i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod. | Eric Anholt | |
| It instead sensibly appears in the src0 slot. | |||
| 2010-10-04 | i965: Add initial folding of constants into operand immediate slots. | Eric Anholt | |
| We could try to detect this in expression handling and do it proactively there, but it seems like less logic to do it in one optional pass at the end. | |||
| 2010-10-04 | i965: Add trivial dead code elimination in the new FS backend. | Eric Anholt | |
| The glsl core should be handling most dead code issues for us, but we generate some things in codegen that may not get used, like the 1/w value or pixel deltas. It seems a lot easier this way than trying to work out up front whether we're going to use those values or not. | |||
| 2010-10-04 | i965: Be more conservative on live interval calculation. | Eric Anholt | |
| This also means that our intervals now highlight dead code. | |||
| 2010-10-03 | i965: Fix glean/texSwizzle regression in previous commit. | Eric Anholt | |
| Easy enough patch, who needs a full test run. Oh, that's right. Me. | |||
| 2010-10-02 | i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE. | Eric Anholt | |
| The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3 | |||
| 2010-10-02 | i965: Add support for EXT_texture_swizzle to the new FS backend. | Eric Anholt | |
| 2010-10-01 | i965: Fix incorrect batchbuffer size in gen6 clip state command. | Kenneth Graunke | |
| FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword. | |||
| 2010-10-01 | i965: Don't try to emit code if we failed register allocation. | Eric Anholt | |
| 2010-10-01 | i965: Fix off-by-ones in handling the last members of register classes. | Eric Anholt | |
| Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately. | |||
| 2010-10-01 | i965: Add a sanity check for register allocation sizes. | Eric Anholt | |
| 2010-10-01 | i965: When producing a single channel swizzle, don't make a temporary. | Eric Anholt | |
| This quickly cuts 8% of the instructions in my glsl demo. | |||
| 2010-10-01 | i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN. | Eric Anholt | |
| By doing so using the register allocator now, we avoid wasting a register to make the alignment happen. | |||
| 2010-10-01 | r600c: fix segfault in evergreen stencil code | Alex Deucher | |
| Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30551 | |||
| 2010-10-01 | savage: Remove unnecessary header. | Vinson Lee | |
| 2010-10-01 | i965: Enable GL_ARB_texture_rg | Ian Romanick | |
| 2010-10-01 | i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4. | Eric Anholt | |
| 2010-10-01 | i965: Add real support for pre-gen5 texture sampling to the new FS. | Eric Anholt | |
| Fixes 36 testcases, including glsl-fs-shadow2d*-bias which fail on the Mesa IR backend. | |||
| 2010-10-01 | evergreen : fix z format setting, enable stencil. | richard | |
| 2010-10-01 | i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS. | Eric Anholt | |
| We should fix the SF to actually give us just the data we need, but this fixes regressions in the new FS until then. Fixes: glsl-kwin-blur glsl-routing | |||
| 2010-10-01 | i965: Also increment attribute location when skipping unused slots. | Eric Anholt | |
| Fixes glsl1-texcoord varying. | |||
| 2010-10-01 | i965: Fix the gen6 jump size for BREAK/CONT in new FS. | Eric Anholt | |
| Since gen5, jumps are in increments of 64 bits instead of increments of 128-bit instructions. | |||
| 2010-10-01 | i965: Add gen6 attribute interpolation to new FS backend. | Eric Anholt | |
| Untested, since my hardware is not booting at the moment. | |||
| 2010-10-01 | r600c: pull over 6xx/7xx vertex fixes for evergreen | Alex Deucher | |
| 2010-09-30 | i965: Split the gen4 and gen5 sampler handling apart. | Eric Anholt | |
| Trying to track the insanity of the different argument layouts for normal/shadow crossed with normal/lod/bias one generation at a time is enough. Fixes: glsl1-texture2D() with bias. (first test passing in this code that doesn't pass without it!) | |||
| 2010-09-30 | i965: Use the lowering pass for texture projection. | Eric Anholt | |
| We should end up with the same code, but anyone else with this issue could share the handling (which I got wrong for shadow comparisons in the driver before). | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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