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path: root/src/mesa/drivers/dri
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2010-07-26i965: Allow VS MOVs to use immediate constants.Eric Anholt
Clarifies program assembly, and with a little tweak to always use constant_map, we could cut down on constant buffer payload.
2010-07-23i965: Cleanly fail programs with unsupported array access.Eric Anholt
This should be more useful for developers and for bug triaging than just generating wrong code.
2010-07-23i965: Add support for VS relative addressing of temporary arrays.Eric Anholt
Fixes glsl-vs-arrays. Bug #27388.
2010-07-22i965: Respect VS/VP point size result when enabled.Eric Anholt
Fixes glsl-vs-point-size.
2010-07-22i965: Fix the disasm output for da16 src widths.Eric Anholt
This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space.
2010-07-22i965: Avoid extra MOV in VS indirect register reads.Eric Anholt
2010-07-22i965: Fix up VS temporary array access for fixed index offset != 0.Eric Anholt
2010-07-22r600: Flip point sprite coordinates when rendering to an FBO.Henri Verbeet
This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
2010-07-21i965: In the VS, multiply the address reg by the appropriate register size.Eric Anholt
The ARL value is increments of vec4 in the register file. But PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved between the two verts being executed (thus a vec8 each), compared to PROGRAM_STATE_VAR being packed vec4s. Fixes: glsl-vs-arrays-2 glsl-vs-mov-after-deref (without regressing glsl-vs-arrays-3)
2010-07-21i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt
2010-07-21i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt
The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets.
2010-07-21i965: Fix the DP read msg_control definitions other than plain OWORD.Eric Anholt
2010-07-21i965: Clean up dead code from the VS get_constant/get_reladdr_constant split.Eric Anholt
2010-07-21i956: Set the execution size correctly for scratch space writes.Eric Anholt
Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders.
2010-07-21i965: Set the GEM domain flags for the scratch space.Eric Anholt
They go into the render cache, so while we don't care about their contents after execution, failing to note them could cause the writes to be flushed over important buffer contents later.
2010-07-21i965: Use the pretty define for 4-oword DP reads.Eric Anholt
2010-07-21i965: Set the send commit bit on register spills as required pre-gen6.Eric Anholt
Otherwise, the subsequent read may not get the written value.
2010-07-21i965: Add disasm for dataport reads (register unspilling).Eric Anholt
2010-07-21i965: Remove an unused variable.Carl Worth
To quiet a compiler warning.
2010-07-20radeon: Remove unnecessary header.Vinson Lee
2010-07-19glx: Remove support for MESA_swap_frame_usageKristian Høgsberg
The extension never worked, the implementation returns GLX_BAD_CONTEXT when enabling the frame tracking.
2010-07-19glx: Drop support for GLX_MESA_allocate_memoryKristian Høgsberg
Only r200 implemented it.
2010-07-19i965: Mostly fix glsl-max-varyings.Eric Anholt
There was confusion on both the size of message we can send, and on what the URB destination offset means. The remaining problems appear to be due to spilling of regs in the fragment shader being broken.
2010-07-19i965: Clean up message register setup in emit_vertex_write().Eric Anholt
2010-07-19i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt
This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results.
2010-07-19i965: Clarify the nr_regs calculation in brw_clip.cEric Anholt
2010-07-19i965: Don't set up VUE space for the disabled user clip distances on gen6.Eric Anholt
2010-07-15r600: fix typo in r700 assemblerAlex Deucher
Noticed by Henri Verbeet on IRC. NOTE: This is a candidate for the 7.8 branch.
2010-07-15radeon: Also flush if it's not the current context that's being destroyed.Henri Verbeet
This avoids calling radeonFlush() during context destruction, when ctx->DrawBuffer would be NULL. NOTE: This is a candidate for the 7.8 branch.
2010-07-15radeon: allow driconf vblank settings with dri2Alex Deucher
fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28771 NOTE: This is a candidate for the 7.8 branch.
2010-07-14r300/compiler: fix swizzling in the transformation of Abs modifiersMarek Olšák
2010-07-13r300/compiler: implement the Abs source operand modifier for vertex shadersMarek Olšák
2010-07-13r300/compiler: emulate SIN/COS/SCS in r3xx-r4xx vertex shadersMarek Olšák
Despite the docs, the corresponding hardware instructions are r5xx-only.
2010-07-12Merge branch 'master' of git://anongit.freedesktop.org/mesa/mesaMaciej Cencora
2010-07-12r600: Fix include recursion.Vinson Lee
Fix r600_context.h -> r700_oglprog.h -> r600_context.h include recursion.
2010-07-12radeon: fix some wine d3d9 testsMaciej Cencora
Need to flush command stream before mapping texture image that is referenced by current cs. Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11radeon: lower texture memory consumption is some casesMaciej Cencora
When searching for valid miptree check images in range of [BaseLeve, MaxLevel] not [MinLod, MaxLoad]. Prevents unnecessary miptree allocations in cases when during every rendering operation different texture image level was selected using MIN_LOD = MAX_LOD = level (for every level new miptree for whole texture was allocated). Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11radeon: fix teximage migration failure in rare caseMaciej Cencora
Always store selected miptree in texObj->mt so get_base_teximage_offset returns correct data. Found with piglit/mipmap-setup. Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11r300c: Fix vertex data setup for named buffer objects with unaligned offsetMaciej Cencora
Candidate for 7.8 branch Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
2010-07-11r600: Remove unnecessary headers.Vinson Lee
2010-07-10r600: Fix GCC 'implication declaration of function' warnings.Vinson Lee
Fix GCC 'implicit declaration of function' compiler warnings resulting from commit 00fb58ed5d7104e675fe48d84e5049e5f7dbb9d7.
2010-07-09r600: Remove unnecessary header.Vinson Lee
Fixes r600_emit.h -> r600_cmdbuf.h -> r600_emit.h include recursion.
2010-07-09r600: Fix include recursion.Vinson Lee
r700_chip.h included r600_context.h, which included r700_chip.h. Remove the unnecessary r600_context.h inclusion and add missing headers.
2010-07-09mesa: Move [UN]CLAMPED_FLOAT_TO_UBYTE from imports.h to macros.h.Vinson Lee
The other similar integer/float conversion macros are in macros.h.
2010-07-08r300/compiler: Add a register rename pass.Tom Stellard
This pass renames register in order to make it easier for the pair scheduler to group TEX instructions together. This fixes fdo bug #28606
2010-07-08r300/compiler: Fix scheduling of TEX instructions.Tom Stellard
The following instruction sequence will no longer be emitted in separate TEX blocks: 0: TEX temp[0].xyz, temp[1].xy__, 2D[0]; 1: TEX temp[1].xyz, temp[2].xy__, 2D[0]; This fixes fdo bug #25109
2010-07-08i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
When EU executes 'wait' instruction, it stalls and sets notification register state. Host can issue MMIO write to clear notification register state to allow EU continue on executing again. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-07-08i965: Fix disasm of a SEND's mlen and rlen on Ironlake.Eric Anholt
2010-07-08i965: Add decode for Sandybridge DP write messages.Zhenyu Wang
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