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2009-09-22r300: Fix crash reported in bug #24066Nicolai Hähnle
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-21radeon: update buffer map/unmap code for changes introduced in ↵Maciej Cencora
92033a9516942d7272ce4bf36ecd422009bbaf60 and 822c7964819ca1fcc270880d4ca8b3de8a4276d0
2009-09-21r300: fix a typoMaciej Cencora
2009-09-21r300: Zero-initialize register for NV_vertex_programNicolai Hähnle
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-21r300: Fix handling of NV_vertex_program parametersNicolai Hähnle
The handling is a bit inefficient, unfortunately, but I don't want to make any intrusive changes for Mesa 7.6. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-21Merge branch 'mesa_7_5_branch' into mesa_7_6_branchMichel Dänzer
2009-09-21intel: Fix crash in intel_flush().Michel Dänzer
Since commit 2921a2555d0a76fa649b23c31e3264bbc78b2ff5 ('intel: Deassociated drawables from private context struct in intelUnbindContext'), intel->driDrawable may be NULL in intel_flush().
2009-09-20radeon: Fix legacy bo not to reuse dma buffers before refcount is 1.Pauli Nieminen
This should help detecting possible memory leaks with dma buffers and prevent possible visual corruption if data would be overwriten too early.
2009-09-20r300/compiler: Fix trig instructions in R300 fpNicolai Hähnle
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-20radeon: Fix typo in variable name.Pauli Nieminen
2009-09-20radeon: Improve WARN_ONCE macro to appear as single statement.Pauli Nieminen
Do-while makes macro safe to be used with if and for constructions. Also remove __LINE__ macro from variable name because scope is local to macro anyway.
2009-09-20radeon: Fix "verts" debugging enableNicolai Hähnle
Copy'n'paste apparently prevented the RADEON_VERTS flag from being enabled. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-20r300/compiler: Fix R300 fragment program regression introduced by 0723cd1...Nicolai Hähnle
We obviously need to move the code addr register backwards because their may be overlap. This bug affected in particular the Compiz water plugin. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-18[i965] add a missing header fileZou Nan hai
2009-09-18 [i965] use intel_batchbuffer_flush to flush the clearZou Nan hai
2009-09-16Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/main/dlist.c
2009-09-16intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick
The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a context. However, the intel_context structure keeps cached copies of these pointers. If these cached pointers are not NULLed and the drawable is actually destroyed after unbinding the context (typically by way of glXDestroyWindow), freed memory will be dereferenced in intelDestroyContext. This should fix bug #23418.
2009-09-16i965: do a flush in clear, fix openarena render issue,Zou Nan hai
fd.o bug# 23857
2009-09-11radeon: Remove structure allocation from iterator variable.Pauli Nieminen
dma_bo varaible is only used for iterating so allocating memory for it only causes memory leaks.
2009-09-10intel: disable intel_stencil_drawpixels() for nowBrian Paul
It doesn't work reliably even when all the prerequisite checks are made.
2009-09-10Fix merge failIan Romanick
One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <brianp@vmware.com> Date: Wed Sep 9 08:33:39 2009 -0600
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/drivers/dri/intel/intel_context.c
2009-09-10i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
2009-09-10intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
2009-09-10radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen
Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
2009-09-09radeon: Add more verbose error message for failed command buffer.Pauli Nieminen
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-08i965: fix incorrect test for vertex position attributeBrian Paul
2009-09-04i965: Fix warnings in intel_pixel_read.c.Eric Anholt
(cherry picked from commit c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)
2009-09-04intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
(cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
2009-09-04intel: Update Mesa state before span setup in glReadPixels.Eric Anholt
We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
2009-09-04intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt
(cherry picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)
2009-09-04i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
(cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
2009-09-04intel: Align cubemap texture height to its padding requirements.Eric Anholt
(cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
2009-09-04intel: Align untiled region height to 2 according to 965 docs.Eric Anholt
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
2009-09-04i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt
For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
2009-09-04i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
2009-09-04i965: asst clean-ups, etc in brw_vs_emit()Brian Paul
(cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
2009-09-04i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt
Previously, we'd be branching based on whatever condition code happened to be laying around. (cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
2009-09-04i965: Spell "conditional" correctly.Eric Anholt
2009-09-04i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt
Bug #20821 (cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
2009-09-04i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt
This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911. (cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
2009-09-04i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt
See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
2009-09-04i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt
This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
2009-09-04i965: Don't emit bad packets when no VBs are referenced.Eric Anholt
It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
2009-09-04i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt
The code duplication bothered me. (cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
2009-09-04i965: Set the max index buffer address correctly according to the docs.Eric Anholt
It's the last addressable byte, not the byte after the end of the buffer. (cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
2009-09-04i965: rename var: s/tmp/vs_inputs/Brian Paul
(cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
2009-09-04r600: fix Elts handlingAlex Deucher
Patch from taiu on IRC. fixes bug 23585
2009-09-03r600: rework cb/db setupAlex Deucher
Setup the regs when we emit rather than during state setup. In certain cases a proper CB target was never emitted. This fixes bug 23658.
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