| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-11-10 | i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile. | Eric Anholt | |
| For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase). | |||
| 2009-11-10 | i965: Add a note explaining the data cache domain. | Eric Anholt | |
| 2009-11-10 | i965: Unalias src/dst registers for SGE and friends. | Eric Anholt | |
| Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 | |||
| 2009-11-10 | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp. | Eric Anholt | |
| Fixes piglit arl.vp. | |||
| 2009-11-09 | r600/r700: typo, fix mask of DB_ALPHA_TO_MASK | Jerome Glisse | |
| 2009-11-09 | r600: rework DB render setup | Alex Deucher | |
| - consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z | |||
| 2009-11-09 | r600: don't emit htile regs | Alex Deucher | |
| These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm. | |||
| 2009-11-09 | r600: add missing ZPASS setup bits for r7xx+ | Alex Deucher | |
| 2009-11-06 | i965: Use Compr4 instruction compression mode on G4X and newer. | Eric Anholt | |
| No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size. | |||
| 2009-11-06 | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
| 2009-11-06 | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
| This should fix issues with antialiased lines in GLSL. | |||
| 2009-11-06 | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst. | |||
| 2009-11-06 | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
| 2009-11-06 | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. | Eric Anholt | |
| 2009-11-06 | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| 2009-11-06 | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c | Eric Anholt | |
| 2009-11-06 | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. | Eric Anholt | |
| 2009-11-06 | i965: Use a normal alu1 emit for OPCODE_TRUNC. | Eric Anholt | |
| 2009-11-06 | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c | Eric Anholt | |
| This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain. | |||
| 2009-11-06 | i965: Collect GLSL src/dst regs up in generic code. | Eric Anholt | |
| This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced. | |||
| 2009-11-06 | intel: better front color buffer test in intelClear() | Brian Paul | |
| 2009-11-06 | i965: Always pass the size argument to brw_cache_data. | Eric Anholt | |
| This keeps the individual state files from having to export their structures for brw_state_cache initialization. | |||
| 2009-11-06 | intel: Finish removing the fallback code for bug #16697. | Eric Anholt | |
| I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54. | |||
| 2009-11-06 | intel: Don't validate in a texture image used as a render target. | Eric Anholt | |
| Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation. | |||
| 2009-11-06 | intel: Clean up some extra struct indirection in finalize. | Eric Anholt | |
| 2009-11-06 | intel: Use _mesa_get_current_tex_object() to clean up TFP path. | Eric Anholt | |
| 2009-11-06 | intel: Remove duplicated arguments from intel_miptree_match_image(). | Eric Anholt | |
| 2009-11-06 | i965: Remove an XXX comment for testing some code that seems to work. | Eric Anholt | |
| 2009-11-06 | intel: Remove obsolete comment about GEM in the spans code. | Eric Anholt | |
| 2009-11-06 | intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing. | Eric Anholt | |
| This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary. | |||
| 2009-11-06 | Make a convenient int for what chipset generation we're on. | Eric Anholt | |
| gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks. | |||
| 2009-11-06 | intel: call intel_check_front_buffer_rendering() in intelClear() | Brian Paul | |
| fixes bug 24953. | |||
| 2009-11-04 | r600: rework draw functions | Alex Deucher | |
| Seems INDX_OFFSET doesn't work properly on some cards, so change back to immediate mode indices. Seems to only affect DRI1. Needs more investigation. Rework and clean up the draw functions. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
| 2009-11-04 | r600: fix count prediction for IB case | Alex Deucher | |
| Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
| 2009-11-04 | Fix YTILE spantmp functions | Alan Hourihane | |
| 2009-11-03 | Merge branch 'mesa_7_6_branch' | Brian Paul | |
| 2009-11-03 | intel: avoid unnecessary front buffer flushing/updating | Brian Paul | |
| Before, if we just called glXMakeCurrent() and didn't render anything we'd still trigger a flushFrontBuffer() call. Now only set the intel->front_buffer_dirty field at state validation time just before we draw something. NOTE: additional calls to intel_check_front_buffer_rendering() might be needed if I missed some rendering paths. | |||
| 2009-11-02 | r600: implement LOG op in compiler | Pierre Ossman | |
| 2009-11-02 | r600: implement EXP op in compiler | Pierre Ossman | |
| 2009-10-31 | radeon: add missing include | Dave Airlie | |
| 2009-10-31 | radeon: use _mesa_get_current_tex_unit | Dave Airlie | |
| 2009-10-30 | intel: Use GTT mapping when available for swrast. | Eric Anholt | |
| This improves piglit quick.tests runtime from 19:33 minutes to 6:06 on my GM45. It should also hide most of the A17 swizzling issues, though they'll still exist when swapping occurs (which is the kernel's problem either way). | |||
| 2009-10-30 | intel: Fix up z24_x8 depth spans since the texformat merge. | Eric Anholt | |
| 2009-10-30 | i965: Add an index assert on get_fp_inst array like other compiler arrays. | Eric Anholt | |
| 2009-10-30 | i965: Fix BRW_WM_MAX_INSN to reflect current limits. | Eric Anholt | |
| Part of fixing bug #24355. | |||
| 2009-10-30 | intel: Set the texture format in the TFP path. | Eric Anholt | |
| This fixes a regression in piglit's tfp test as of 11caea687e3f10ae12d33e44edf84635f73047dd. Additionally, set the texture format for the RGB textures to MESA_FORMAT_XRGB8888 and support it in the hw paths so that hopefully sw fallbacks involving TFP get better alpha behavior. The radeon drivers appear to need the same fix. Bug #24803 | |||
| 2009-10-30 | r600: remove duplicate line | Alex Deucher | |
| 2009-10-30 | r600: fill in some missing tex formats | Alex Deucher | |
| This improves shadowtex since the component ordering is at least correct now, but I'm not sure how to deal with texturing from a depth surface yet due to differences in depth and color tile layouts. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
| 2009-10-30 | r600: fix a warning, update comments | Alex Deucher | |
| 2009-10-30 | r600: use AUTO_INDEX for draw - saves cmd buffer space | Andre Maasikas | |
| also seems we can use INDX_OFFSET if start != 0 | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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