Age | Commit message (Collapse) | Author |
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Mixing stderr (_mesa_print_program, _mesa_print_instruction,
_mesa_print_alu) with stdout means that when writing both to a file,
there isn't a consistent ordering between the two.
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This pulls in multiple i965 driver fixes which will help ensure better
testing coverage during development, and also gets past the conflicts
of the src/mesa/shader -> src/mesa/program move.
Conflicts:
src/mesa/Makefile
src/mesa/main/shaderapi.c
src/mesa/main/shaderobj.h
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Also fix up comments, so that the difference between the two passes is
clarified.
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Several routines directly analyze the grf-to-mrf moves from the Gen
binary code. When it is possible, the mov is removed and the message
register is directly written in the arithmetic instruction
Also redundant mrf-to-grf moves are removed (frequently for example,
when sampling many textures with the same uv)
Code was tested with piglit, warsow and nexuiz on an Ironlake
machine. No regression was found there
Note that the optimizations are *deactivated* on Gen4 and Gen6 since I
did test them properly yet. No reason there are bugs but who knows
The optimizations are currently done in branch free programs *only*.
Considering branches is more complicated and there are actually two
paths: one for branch free programs and one for programs with branches
Also some other optimizations should be done during the emission
itself but considering that some code is shader between vertex shaders
(AOS) and pixel shaders (SOA) and that we may have branches or not, it
is pretty hard to both factorize the code and have one good set of
strategies
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Clarifies program assembly, and with a little tweak to always use
constant_map, we could cut down on constant buffer payload.
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This should be more useful for developers and for bug triaging than
just generating wrong code.
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Fixes glsl-vs-arrays. Bug #27388.
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Fixes glsl-vs-point-size.
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This has confused me twice now. It's a fixed width of 4 (usually a
region description of <4,4,1>), not 1. If it was 1, we'd have been
skipping all over register space.
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This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
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The ARL value is increments of vec4 in the register file. But
PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved
between the two verts being executed (thus a vec8 each), compared to
PROGRAM_STATE_VAR being packed vec4s.
Fixes:
glsl-vs-arrays-2
glsl-vs-mov-after-deref
(without regressing glsl-vs-arrays-3)
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The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
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Otherwise, the second half isn't written, and we end up reading back
black.
Fixes the remaining junk drawn in glsl-max-varyings, and will likely
help with a number of large real-world shaders.
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They go into the render cache, so while we don't care about their
contents after execution, failing to note them could cause the writes
to be flushed over important buffer contents later.
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Otherwise, the subsequent read may not get the written value.
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To quiet a compiler warning.
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The extension never worked, the implementation returns GLX_BAD_CONTEXT
when enabling the frame tracking.
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Only r200 implemented it.
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There was confusion on both the size of message we can send, and on
what the URB destination offset means.
The remaining problems appear to be due to spilling of regs in the
fragment shader being broken.
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This cleans up some chipset dependency sprinkled around, and fixes a
potential overflow of the attribute offset array for many vertex
results.
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Noticed by Henri Verbeet on IRC.
NOTE: This is a candidate for the 7.8 branch.
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This avoids calling radeonFlush() during context destruction, when
ctx->DrawBuffer would be NULL.
NOTE: This is a candidate for the 7.8 branch.
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fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28771
NOTE: This is a candidate for the 7.8 branch.
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Despite the docs, the corresponding hardware instructions are r5xx-only.
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Fix r600_context.h -> r700_oglprog.h -> r600_context.h include
recursion.
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Need to flush command stream before mapping texture image
that is referenced by current cs.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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When searching for valid miptree check images in range
of [BaseLeve, MaxLevel] not [MinLod, MaxLoad].
Prevents unnecessary miptree allocations in cases when during
every rendering operation different texture image level
was selected using MIN_LOD = MAX_LOD = level (for every level
new miptree for whole texture was allocated).
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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