| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-08-12 | radeon: Minor warnings cleanup. | Eric Anholt | |
| 2009-08-12 | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds. | Eric Anholt | |
| 2009-08-12 | radeon: Add protection against recursive DRM locking. | Pauli Nieminen | |
| Reference counting protects DRM lock call from recursive locking that would cause hang. Code also adds optional debugging output for recursive call that is compiled only if NDEBUG is not defined. This code is not 100% thread safe because mesa doesn't include increment and test atomic operation. There is built-in gcc functions but they are only available from gcc 4.2. | |||
| 2009-08-12 | r600: A shader is bound that exports Z as a float into Red channel | Cooper Yuan | |
| 2009-08-11 | r600: use the drm ioctls for swap and texture upload | Alex Deucher | |
| NOTE: THIS REQUIRES AN UPDATED DRM! | |||
| 2009-08-11 | mesa/glapi: regenerated files from gl_API.xml | Brian Paul | |
| 2009-08-11 | r600: update num of interp if posizition is used | Cooper Yuan | |
| 2009-08-10 | intel: use new _mesa_meta_copy_pixels() function | Brian Paul | |
| glCopyPixels() no longer hits a software fallback when zooming, blending, etc. | |||
| 2009-08-10 | intel: add missing \n to fprintf() | Brian Paul | |
| 2009-08-10 | intel: use new _mesa_meta_blit_framebuffer() function | Brian Paul | |
| The previous version of framebuffer blit was a quick hack. The new meta version works pretty well. | |||
| 2009-08-10 | radeon_fbo: switch short to byte for 565 | Dave Airlie | |
| 2009-08-10 | radeon: fix cut-n-paste in alphabits in fbo code | Dave Airlie | |
| 2009-08-09 | r600: looks like a typo | Dave Airlie | |
| 2009-08-09 | r600: load per-pixel position into PS in order to use fragment.position. | Cooper Yuan | |
| This patch can fix /progs/fp/tri-depth, tri-depth2, tri-depthwrite, tri-depthwrite2 and point-position. | |||
| 2009-08-07 | Revert "i965: Disable texture tiling by default." | Eric Anholt | |
| This reverts commit b8e638d4895d2d342306bb6443a455f73903ce20. Now that the known hangs and misrendering issues are fixed, I'm ready to start encouraging it by default again. | |||
| 2009-08-07 | intel: Align region height as required for tiled regions. | Eric Anholt | |
| Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406. | |||
| 2009-08-07 | i965: Add a note justifying domain choice for the SF VP. | Eric Anholt | |
| 2009-08-07 | intel: Add some more safety asserts in the blit code. | Eric Anholt | |
| 2009-08-07 | i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP. | Eric Anholt | |
| This showed a 1.9% (+/-.3%, n=3) improvement in OA performance with high geometry settings. | |||
| 2009-08-07 | radeon: correct fix for tiling with the legacy build | Alex Deucher | |
| 2009-08-07 | intel: Fix googleearth by avoiding GL_VIEWPORT_BIT in meta clear push/pop | Eric Anholt | |
| I have no idea why this fixes things, but being more efficient sounds good anyway. Fixes regression in 99d07d0f91ddd37926d08f4e7f10d55cac28d9a7 where most of the lit half of the world was not drawn. | |||
| 2009-08-07 | radeon: fix the build with older drm headers | Alex Deucher | |
| 2009-08-07 | dri: Fix problems with unitialized values in dri screen object. | Pauli Nieminen | |
| This fixes crash in r200 KMS driver when pSAREA was set to 1 randomly because of memory wasn't cleared. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> | |||
| 2009-08-07 | i965: minor context comments | Brian Paul | |
| 2009-08-07 | intel: minor context comments | Brian Paul | |
| 2009-08-07 | intel: move blit call out of assert() | Brian Paul | |
| 2009-08-07 | intel: fix typo: s/softare/software/ | Brian Paul | |
| 2009-08-07 | radeon: enable tiling fallbacks in 3D driver. | Dave Airlie | |
| Only really got good testing on r500 so far, need to enable in DDX and play some more. | |||
| 2009-08-07 | radeon span: add r200 depth/stencil span read/writing | Dave Airlie | |
| this should only really affect DRI2 since we mostly have a surface in DRI1. I don't think this is perfect yet, but it is a better start than nothing. | |||
| 2009-08-07 | r200: fix scissor emission for r200 under kms | Dave Airlie | |
| 2009-08-06 | mesa: Ignores | Jakob Bornecrantz | |
| Got tired of seeing these files in git status all the time | |||
| 2009-08-05 | i965: Fix source depth reg setting for FSes reading and writing to depth. | Eric Anholt | |
| For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. | |||
| 2009-08-05 | Merge branch 'mesa_7_5_branch' | Brian Paul | |
| Conflicts: src/mesa/main/state.c | |||
| 2009-08-05 | r200: emit colorpitch | Dave Airlie | |
| 2009-08-04 | i965: Fix dangerous warning I let slip in. | Eric Anholt | |
| 2009-08-04 | i965: Respect CondSwizzle in OPCODE_IF. | Eric Anholt | |
| Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 | |||
| 2009-08-04 | i965: Emit conditional code updates as required for GLSL VS if statements. | Eric Anholt | |
| Previously, we'd be branching based on whatever condition code happened to be laying around. | |||
| 2009-08-04 | i965: Don't set pop_count in the reserved MBZ area of IF statements. | Eric Anholt | |
| 2009-08-04 | i965: Print out ELSE and ENDIF src1 arguments like IF does. | Eric Anholt | |
| 2009-08-05 | r200: fix off-by-one errors causing 6th texture unit to not work | Roland Scheidegger | |
| both for normal and cube textures, this fixes demos/multiarb (with 6 enabled texture units) and fixes #23142. | |||
| 2009-08-05 | r200: fix compiler warning (unused var) | Roland Scheidegger | |
| 2009-08-05 | radeon: fix miptree comparison breakage | Roland Scheidegger | |
| another case of image never matching miptree in case of compressed textures | |||
| 2009-08-05 | intel: implement intelCompressedTexSubImage2D | Roland Scheidegger | |
| similar to the radeon code. passes tests/texcompsub | |||
| 2009-08-04 | intel: Add support for EXT_provoking_vertex. | Eric Anholt | |
| 2009-08-04 | i965: Spell "conditional" correctly. | Eric Anholt | |
| 2009-08-04 | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}. | Eric Anholt | |
| I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it. | |||
| 2009-08-04 | i965: Initial import of disasm code from intel-gen4asm. | Eric Anholt | |
| There's a bunch of stuff from gen4asm and gpu-tools that we probably want to make into a library instead of cargo-culting it around. | |||
| 2009-08-04 | i965: warning fix | Eric Anholt | |
| 2009-08-04 | i965: Fix RECT shadow sampling by not losing the other texcoords. | Eric Anholt | |
| Bug #20821 | |||
| 2009-08-04 | intel: Fix inverted test for disabling flushing of front buffer output. | Brian Paul | |
| The comment disagreed with the code, and nicely drew my eyes to what was going wrong. Bug #21774 (blender) Bug #21788 (readpix) (cherry picked from master, commit fd65418f600874b05f902b622078b40bc1abb24a) | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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