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FEATURE_accum, FEATURE_convolve, FEATURE_colortable, and FEATURE_drawpix
cover part of the functionalities of swrast module. Disable them when
the features are disabled.
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_tnl_RasterPos should be disabled with FEATURE_rastpos.
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Previously, it was trying to mess around with the varying's
WM setup data to produce a result. Along with not actually working when
passed a varying, this wouldn't work if you did dFd[xy]() on a temporary.
Instead, just calculate the derivative using the neighbors in the subspan.
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with some minor updates from Richard.
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This reverts commit 4099bb76148007f9ccb6c86838b2bf37ea42de56.
Tex coord src has to be a GPR.
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Fixes neverball among other things.
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Passes piglit glsl-vs-loop testcase.
Bug #20171
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It doesn't work reliably even when all the prerequisite checks are made.
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One of the conflicst from this merge was missed:
commit 0c309bb494b6ee1c403442d1207743f749f95b6e
Merge: c6c44bf d27d659
Author: Brian Paul <brianp@vmware.com>
Date: Wed Sep 9 08:33:39 2009 -0600
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Plus, check for pixel transfer stencil index/offset.
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Conflicts:
src/mesa/drivers/dri/intel/intel_context.c
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This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245.
Bug #23688
Bug #23254
(cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Hopefully this will be one of the last cherry-picks.
(cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
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This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
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Variadic functions can't be inlined which makes debugging to have quite large
function overead. Only aleternative method is to use variadic macros which are
inlined so compiler can optimize debugging to minimize overhead.
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This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245.
Bug #23688
Bug #23254
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noticed by taiu on IRC.
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Conflicts:
Makefile
configs/default
progs/glsl/Makefile
src/gallium/auxiliary/util/u_simple_shaders.c
src/gallium/state_trackers/glx/xlib/xm_api.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_pixel.c
src/mesa/drivers/dri/intel/intel_pixel_read.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
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Works around a bug found on i965. See bug 23670.
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We use t->bo for dri1 since r600 uses CS for dri1.
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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if we have a BO here it means TFP and we should have set it
up already.
tested by b0le on #radeon
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On the 965, we just drop the value into the primitive packet. On non-945,
we rely on the sw tnl code handling it.
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The wording of these two is exactly the same, except for the issue
"Can fragments with wc<=0 be generated when this extension is supported?",
which idr thinks is a non-issue for us.
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This currently doesn't include fixing up the cliptests in the assembly
paths to support ARB_depth_clamp, so enabling depth_clamp forces the C path.
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For drawing to lower mipmap levels, the region size makes the renderbuffer
be the size of the lowest level, instead of the current level. On DRI1,
Brian previously found that the RB size was incorrect, so leave this broken
there.
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This reverts commit e0ec405a9fa6fbc1cf2ac531ed5efd1a64e01f18.
This is already available in INTEL_DEBUG=bufmgr in the environment.
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Also, remove unneeded call to _mesa_validate_pbo_access(). It's done by
core Mesa as the comment suggested.
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Incomplete and totally untested. Based on intel_generate_mipmap().
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