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The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
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This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
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This is required for 965 performance, as it avoids a lot of repeated data
uploads of the state caches due to surface offsets in them.
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They shouldn't be created, and this often helps catch stupid issues.
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This is required for 965 support, which has relocations in other places than
just the batchbuffer.
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The lock coverage and checks for cliprects were unneeded since the batchbuffer
will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from
intelClearWithBlit.
This makes the locking requirements of i915 meta_draw_quad match i965
meta_draw_quad.
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this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
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This was replaced in previous releases of xserver/dri/libGL by reporting the
damage to the frontbuffer so that the server and driver could handle it
appropriately.
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This seems to have been mismerged with the DRI interface changes.
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Use symbolic array indices to clarify.
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I've no idea if this code might break something or how it should interact
with vertex shaders, it makes the clip demo work for me
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Thanks to the PS3 RSX project for figuring this out.
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This should restore gears speed on 9xx hardware
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Add entrypoints to glapi XML file and regenerate files.
Implement glStencilOpSeparateATI().
Consolidate some code in stencil.c
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* Fix crash at context creation in most drivers supporting vblank.
* Don't pass vblank sequence or flags to functions that get passed the drawable
private already.
* Attempt to initialize vblank related drawable private fields just once
per drawable. May need more work in some drivers.
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Consolidate support for synchronizing to and retrieving vblank counters. Also
fix the core vblank code to return monotonic MSC counters, which are required
by some GLX extensions. Adding support for multiple pipes to a low level
driver is fairly easy, the Intel 965 driver provides simple example code (see
intel_buffers.c:intelWindowMoved()).
The new code bumps the media stream counter extension version to 2 and adds a
new getDrawableMSC callback. This callback takes a drawablePrivate pointer,
which is used to calculate the MSC value seen by clients based on the actual
vblank counter(s) returned from the kernel. The new drawable private fields
are as follows:
- vblSeq - used for tracking vblank counts for buffer swapping
- vblFlags - flags (e.g. current pipe), updated by low level driver
- msc_base - MSC counter from the last time the current pipe changed
- vblank_base - kernel DRM vblank counter from the last time the pipe changed
Using the above variables, the core vblank code (in vblank.c) can calculate a
monotonic MSC value. The low level DRI drivers are responsible for updating
the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags)
along with msc_base and vblank_base whenever the pipe associated with a given
drawable changes (again, see intelWindowMoved for an example of this).
Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to
driDrawableGetMSC32 and add code for pipe switching as outlined above to fully
support the new scheme.
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Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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Currently only GL_DEPTH_COMPONENT16 are supported. I don't know what the
hardware bits are to select the other formats, but it shouldn't be too hard
to figure out.
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The hardware seems to interpret them differently and produce unexpected
results...
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