| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-07-14 | i915: fix build after previous commit. | Eric Anholt | |
| 2008-07-11 | drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. | Eric Anholt | |
| 2008-07-02 | intel: span rendering requires just a flush before starting, not finish. | Eric Anholt | |
| The dri_bo_map()s that follow will take care of idling the hardware as needed. | |||
| 2008-07-02 | intel-gem: Emit an MI_FLUSH at glFlush() so frontbuffer rendering is flushed. | Eric Anholt | |
| We have something similar in the X Server that covers X Server rendering, this is the equivalent here for rendering to the front buffer. If we cared about avoiding this at glFlush time, we could only do this when some actual frontbuffer rendering had occurred. Bug #16392. | |||
| 2008-07-02 | intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1. | Eric Anholt | |
| Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly. | |||
| 2008-07-02 | intel-gem: Fix Y-tiling span setup. | Eric Anholt | |
| The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8. | |||
| 2008-07-01 | intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode. | Eric Anholt | |
| It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect. | |||
| 2008-06-26 | intel: Fix locking when doing intel_region_cow(). | Eric Anholt | |
| This was broken in the merge of 965 blit support. It tried to lock only when things were already locked. | |||
| 2008-06-26 | intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing. | Eric Anholt | |
| Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock. | |||
| 2008-06-24 | Merge commit 'origin/master' into drm-gem | Eric Anholt | |
| 2008-06-24 | intel: Fix glCopyPixels when x or y are < 0 in hw coordinates. | Eric Anholt | |
| Nothing would get drawn as the negative coordinates broke the rectangle intersection code that used unsigned ints. Tested with copypix demo and sliding the copy to the upper left. | |||
| 2008-06-24 | i965: Use the shared intel_pixel_copy.c. | Eric Anholt | |
| This disables the textured copy implementation on 965, which didn't appear to work (mesa copypix demo, disable the blit path, move so that regions don't overlap and textured is used, and you get garbage). If we resurrect this for i965, I'd rather it used the 915-style metaops instead. Current metaops code left in place so that whoever picks it up has a reference. | |||
| 2008-06-24 | intel: Same pixel function init for everyone now. | Eric Anholt | |
| 2008-06-24 | intel: Avoid glBitmap software fallback for blending when no blending occurs. | Eric Anholt | |
| Mesa demos tend to leave blending on but in GL_ONE/GL_ZERO, or GL_SRC_ALPHA/GL_ONE_MINUS_SRC_ALPHA with a source alpha of 1.0. | |||
| 2008-06-24 | intel: Merge check_blit_fragment_ops between i915/i965. | Eric Anholt | |
| Both had some useful bits for the other. | |||
| 2008-06-24 | intel: Note reasons for blit pixel op fallbacks under INTEL_DEBUG=pix. | Eric Anholt | |
| 2008-06-24 | i915: Add support for accelerated glBitmap, shared from 965. | Eric Anholt | |
| 2008-06-24 | i915: Fix read != draw drawable for glCopyPixels. | Eric Anholt | |
| Taken from commit bad6e175cf59cce630c37d73f6e71f3a4de50ae6. | |||
| 2008-06-24 | i915: Allow accelerated pixel ops to be disabled with INTEL_NO_BLIT. | Eric Anholt | |
| This matches 965. | |||
| 2008-06-23 | i915: Accumulate the VB into a local buffer and subdata it in. | Eric Anholt | |
| This lets GEM use pwrite, for an additional 4% or so speedup. | |||
| 2008-06-23 | i915: Convert to using VBs instead of inline prims. | Eric Anholt | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | #undef DEBUG to silence warnings | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-21 | s/inline/INLINE | Brian Paul | |
| 2008-06-21 | remove old comments | Brian Paul | |
| 2008-06-21 | Solaris port of Mesa 7.1 with autoconf support | Alan Coopersmith | |
| Signed-off-by: Brian Paul <brian.paul@tungstengraphics.com> | |||
| 2008-06-21 | R300: 1002:5657 is actually RV410 | Alex Deucher | |
| See bug 14289 | |||
| 2008-06-21 | r200: fix typo in r200TryDrawPixels parameter validation (bug 16406) | Roland Scheidegger | |
| 2008-06-18 | i915: Note the non-PBO fallback for textured drawpixels under DEBUG_PIXEL. | Eric Anholt | |
| 2008-06-18 | i915: Restore the accelerated PBO pixel path functions after GEM changes. | Eric Anholt | |
| The fencing code is not required, and waiting on the fences defeated one of the purposes of the extension, which is to allow asynchronous readpixels. | |||
| 2008-06-18 | Merge commit 'origin/master' into drm-gem | Eric Anholt | |
| 2008-06-18 | i915: Bug #14313: Fix accelerated (PBO) ReadPixels. | Eric Anholt | |
| Refactoring of mine in 02d5ba849197e19843dad164239b51f18fb16faf broke it by failing to understand that the masking was about sign extension. | |||
| 2008-06-18 | i965: add support for Intel 4 series chipsets | Xiang, Haihao | |
| 2008-06-17 | [intel] Fix no_rast option on non-965. | Eric Anholt | |
| The no_rast fallback was getting partially overwritten by later TNL init, resulting in a segfault when things were in a mixed-up state. | |||
| 2008-06-17 | [intel-gem] Bug #16326: Fix X tile unswizzling on 965. | Eric Anholt | |
| Apparently a bit gets flipped in the addressing for some rows of each tile. | |||
| 2008-06-17 | assorted glide driver fixes | Wilfried Holzke | |
| 2008-06-16 | r300: Make LOD bias a persistent environment variable. | Corbin Simpson | |
| Per airlied's suggestion. | |||
| 2008-06-16 | r300: Fix new incarnation of bug 3195. | Corbin Simpson | |
| tests/bug_3195 doesn't render right, but at least it doesn't segfault this way. | |||
| 2008-06-16 | r300: Forgot to clear old state before writing new state. | Corbin Simpson | |
| Oooops. Hehe. | |||
| 2008-06-15 | r300: Enable LOD bias state emission. | Corbin Simpson | |
| Properly set t->filter_1 for r300_state to emit. Expect buggies as people see LOD bias enabled for the first time... | |||
| 2008-06-15 | Oops, misordered a few instructions. | Corbin Simpson | |
| Not like it matters, though, since it's not taking effect yet. | |||
| 2008-06-15 | r300: Unbreak LOD biasing, a bit. | Corbin Simpson | |
| Needs a bit more work on submission. | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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