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We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order.
We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
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RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
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- when rewriting per component negate swizzle, first instruction should get not negated source
- KIL instruction ignores swizzles
TODO:
- tex instructions does not support saturation
- tex instructions cannot read from consant memory
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Sending from VAP more texture coordinates than RS expects results in GPU hang.
Fixes BumpSelfShadow from DirectX8 SDK.
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If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements.
Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
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If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
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vertices
When with memory manager we need to make sure the GPU won't try to access
beyond vertex buffer size, do so by enforcing that the maximun index is the
last vertex of the buffer.
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This gets the correct srclvl image map when uploading images to the new mipmap.
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Fixes GPU hangs in software TCL path
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Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT.
Fix license header too.
Reported by: Nicolai Hähnle <nhaehnle@gmail.com>
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software TCL path
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Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays.
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Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components.
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autoconf had been designating the 8 bit libOSMesa as the default
standalone osmesa, but the Makefile expected it to be linked to libGL.
Fix up the osmesa Makefile so that it allows any of the combinations of
standalone and channel width to be built.
Fixes bug #21980.
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This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
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We're on the way to telling the kernel about when we need fence regs on our
objects or not, and this will cut the number of places needing them.
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This prevents the width / height from being clipped to the window size before
the texture is allocated. This matches intelCopyTexImage1D.
This should fix bug #21227
Signed-off-by: Ian Romanick <ian.romanick@intel.com>
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This saves doing swtnl from uncached memory, which is painful. Improves
clutter test-text performance by 10% since it started using VBOs.
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This gets two more glean glsl1 tests using the non-GLSL path.
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Display the chip family and PCI ID. This can be parsed easily,
and essentially all information that the driver has about the chip can be
deduced from it.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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The special feature of bin/minstall to copy symlinks is only ever needed
when installing libraries which may have .so symlinks. All the headers
and directories can use a normal install program.
These two modes are separated as $(INSTALL) and $(MINSTALL) to allow the
user (or autoconf) to override installing normal files as they please.
An autoconf check for the install program has been added and will be
used in preference to minstall when available.
Fixes bug 16053.
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Fixes failed viewport updates on glxgears (and other apps) resize since
e41780fedc2c1f22b43118da30a0103fa68b769f.
Bug #20473.
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Limit the maximum renderbuffer size to 8192 on i965 and to 2048 on
earlier hardware.
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To avoid locking bug we shouldn't not call firevertices from this path
as it's call from radeon get lock.
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In DRI1 kernel emit scissor but in dri2 cs path we have to
explicitly program them.
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