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path: root/src/mesa/drivers
AgeCommit message (Expand)Author
2009-09-10intel: add B43 chipset supportZhenyu Wang
2009-09-10radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen
2009-09-09radeon: Add more verbose error message for failed command buffer.Pauli Nieminen
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
2009-09-09mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels()Brian Paul
2009-09-08i965: fix incorrect test for vertex position attributeBrian Paul
2009-09-04i965: Fix warnings in intel_pixel_read.c.Eric Anholt
2009-09-04intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
2009-09-04intel: Update Mesa state before span setup in glReadPixels.Eric Anholt
2009-09-04intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt
2009-09-04i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
2009-09-04intel: Align cubemap texture height to its padding requirements.Eric Anholt
2009-09-04intel: Align untiled region height to 2 according to 965 docs.Eric Anholt
2009-09-04i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt
2009-09-04i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt
2009-09-04i965: asst clean-ups, etc in brw_vs_emit()Brian Paul
2009-09-04i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt
2009-09-04i965: Spell "conditional" correctly.Eric Anholt
2009-09-04i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt
2009-09-04i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt
2009-09-04i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt
2009-09-04i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt
2009-09-04i965: Don't emit bad packets when no VBs are referenced.Eric Anholt
2009-09-04i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt
2009-09-04i965: Set the max index buffer address correctly according to the docs.Eric Anholt
2009-09-04i965: rename var: s/tmp/vs_inputs/Brian Paul
2009-09-04r600: fix Elts handlingAlex Deucher
2009-09-03r600: rework cb/db setupAlex Deucher
2009-09-03r600: make sure the active vertex shader bo is re-added to persistent list.Alex Deucher
2009-09-03mesa: rename gl_sync_object::Status to StatusFlagBrian Paul
2009-09-03Add ARB_sync to the xorg sw dri driver.Eric Anholt
2009-09-03savage: Fix driver build post-ARB_sync.Eric Anholt
2009-09-03s3v: Fix driver build for ARB_sync.Eric Anholt
2009-09-03intel: Add support for ARB_sync.Eric Anholt
2009-09-03ARB sync / swrast: Use GL_ARB_sync_functions instead of GL_ARB_sync. Oops.Ian Romanick
2009-09-03ARB sync: Add support for GL_ARB_sync to swrastIan Romanick
2009-09-03Eliminate trailing whitespace in extension_helper.cIan Romanick
2009-09-03ARB sync: Regenerate files from previous commitIan Romanick
2009-09-03intel: helper to debug bufmgr (disabled)Brian Paul
2009-09-03mesa: change ctx->Driver.BufferData() to return GLboolean for success/failureBrian Paul
2009-09-03r600: visual depth has no meaning here.Dave Airlie
2009-09-03r600: make sure the active shader bo is re-added to persistent list.Dave Airlie
2009-09-03radeon: pass internal format into the miptree.Dave Airlie
2009-09-03radeon/dri2: add gl20 bits for r300/r600 just like dri1 doesDave Airlie
2009-09-02Revert "i965: Use VBOs in the VBO module on 965, now that we have ARB_map_buf...Eric Anholt
2009-09-02intel: Add support for FlushMappedBufferRange for ARB_map_buffer_range.Eric Anholt
2009-09-02intel: Sync a synchronized READ_BIT map buffer range with GL drawing to it.Eric Anholt
2009-09-02intel: Move MapBufferRange mesa state setting up to cover the 915 case.Eric Anholt
2009-09-02i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao
2009-09-02i965: validate sf stateXiang, Haihao
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