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2011-02-10i915: Force lowering of all types of indirect array accesses in the FSIan Romanick
NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-02-10i915: Calculate partial result to temp register firstIan Romanick
Previously the SNE and SEQ instructions would calculate the partial result to the destination register. This would cause problems if the destination register was also one of the source registers. Fixes piglit tests glsl-fs-any, glsl-fs-struct-equal, glsl-fs-struct-notequal, glsl-fs-vec4-operator-equal, glsl-fs-vec4-operator-notequal. NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-02-08r200: add cast to silence warningBrian Paul
2011-02-08mesa: remove _mesa_create_context_for_api()Brian Paul
Just add the gl_api parameter to _mesa_create_context().
2011-02-08mesa: remove _mesa_initialize_context_for_api()Brian Paul
Just add the gl_api parameter to _mesa_initialize_context().
2011-02-08i965: Add missing DEFINE_BITS for brw dirty bits.Kenneth Graunke
These are only used for debugging, but should be there. Found by inspection.
2011-02-08i965: Separate the BRW_NEW_(VS|WM)_CONSTBUF dirty bits.Kenneth Graunke
These were incorrectly defined to the same value - likely due to a cut and paste error. Found by inspection.
2011-02-08i965: Rename a few more commands to match the documentation.Kenneth Graunke
2011-02-08i965: Remove pointless keying of WM state on VUE size.Eric Anholt
2011-02-07intel: Implement dri2::{Allocate,Release}BufferBenjamin Franzke
2011-02-07Add dri2::{Allocate,Release}Buffer extensionBenjamin Franzke
2011-02-05r300/compiler: Disable register rename pass on r500Tom Stellard
The scheduler and the register allocator are not good enough yet to deal with the effects of the register rename pass. This was causing a 50% performance drop in Lightsmark. The pass can be re-enabled once the scheduler and the register allocator are more mature. r300 and r400 still need this pass, because it prevents a lot of shaders from using too many texture indirections. NOTE: This is a candidate for the 7.10 branch.
2011-02-05r300/compiler: Don't count BEGIN_TEX instructions in the compiler statsTom Stellard
2011-02-05mesa/965: add support for GL_EXT_framebuffer_sRGB (v2)Dave Airlie
This adds i965 support for GL_EXT_framebuffer_sRGB, it introduces a new constant to say that the driver can support sRGB enabled FBOs since enabling the extension doesn't mean the driver can actually support sRGB. Also adds the suggested state flush in the core code suggested by Brian. fix the ARB_fbo color encoding. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-04i965: Drop the dead tracking of color_regions[].Eric Anholt
We pull the draw regions right out of the renderbuffers these days.
2011-02-04i965: Drop the INTEL_DEBUG=state spam about the cache size check.Eric Anholt
There's way more interesting info in INTEL_DEBUG=state if you could find it among the state size checks.
2011-02-03swrast: add an interface createNewContextForAPIHaitao Feng
This new interface could set up context for OpenGL, OpenGL ES1 and OpenGL ES2. It will be used by egl_dri2 driver. Signed-off-by: Haitao Feng <haitao.feng@intel.com>
2011-02-03r300c: Unbreak after R4xx support was added to r300/compiler.Michel Dänzer
2011-02-01r200: remove 0x4243 pci idAlex Deucher
There's no such device. 0x4243 is a pci bridge id, not a GPU. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-01i915: Only mark a register as available if all components are writtenIan Romanick
Previously a register would be marked as available if any component was written. This caused shaders such as this: 0: TEX TEMP[0].xyz, INPUT[14].xyyy, texture[0], 2D; 1: MUL TEMP[1], UNIFORM[0], TEMP[0].xxxx; 2: MAD TEMP[2], UNIFORM[1], TEMP[0].yyyy, TEMP[1]; 3: MAD TEMP[1], UNIFORM[2], TEMP[0].zzzz, TEMP[2]; 4: ADD TEMP[0].xyz, TEMP[1].xyzx, UNIFORM[3].xyzx; 5: TEX TEMP[1].w, INPUT[14].xyyy, texture[0], 2D; 6: MOV TEMP[0].w, TEMP[1].wwww; 7: MOV OUTPUT[2], TEMP[0]; 8: END to produce incorrect code such as this: BEGIN DCL S[0] DCL T_TEX0 R[0] = MOV T_TEX0.xyyy U[0] = TEXLD S[0],R[0] R[0].xyz = MOV U[0] R[1] = MUL CONST[0], R[0].xxxx R[2] = MAD CONST[1], R[0].yyyy, R[1] R[1] = MAD CONST[2], R[0].zzzz, R[2] R[0].xyz = ADD R[1].xyzx, CONST[3].xyzx R[0] = MOV T_TEX0.xyyy U[0] = TEXLD S[0],R[0] R[1].w = MOV U[0] R[0].w = MOV R[1].wwww oC = MOV R[0] END Note that T_TEX0 is copied to R[0], but the xyz components of R[0] are still expected to hold a calculated value. Fixes piglit tests draw-elements-vs-inputs, fp-kill, and glsl-fs-color-matrix. It also fixes Meego bugzilla #13005. NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-01-31i965: Emit texel offsets in sampler messages.Kenneth Graunke
2011-01-31Remove talloc from the make and automake build systems.Kenneth Graunke
2011-01-31Convert everything from the talloc API to the ralloc API.Kenneth Graunke
2011-01-29r300/compiler: Standardize the number of bits used by swizzle fieldsTom Stellard
Swizzles are now defined everywhere as a field with 12 bits that contains 4 channels worth of meaningful information. Any channel that is unused is set to RC_SWIZZLE_UNUSED. This change is necessary because rgb instructions and alpha instructions were initializing channels that would never be used (channel 3 for rgb and channels 1-3 for alpha) with 0 (aka RC_SWIZZLE_X). This made it impossible to use generic helper functions for swizzles, because sometimes a channel value of 0 meant unused and other times it meant RC_SWIZZLE_X. All hacks that tried to guess how many channels were relevant have also been removed.
2011-01-28r300/compiler: print stats based on the initial number of instructionsMarek Olšák
The same number of shaders is now printed regardless of optimizations being enabled or not, so that we can compare shader stats side by side easily.
2011-01-24mesa: plug in fallback function for ctx->Driver.ValidateFramebuffer()Brian Paul
The software renderer doesn't support GL_ALPHA, GL_LUMINANCE, etc so we should report GL_FRAMEBUFFER_UNSUPPORTED during FBO validation.
2011-01-24osmesa: mklib requires arguments before objectsChristopher James Halse Rogers
Fixes the build when selecting driver=osmesa and building static libraries. Otherwise, mklib tries to add the ‘-ltalloc’ object to the archive, which obviously fails. Clients which statically link to osmesa will need to link to libtalloc also, as specified in the Libs.private of osmesa.pc. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33360 NOTE: This is a candidate for the 7.10 branch. Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com> Signed-off-by: Brian Paul <brianp@vmware.com>
2011-01-24r600c: only colors can be flat shadedAndre Maasikas
fixes stellarium text and menu display
2011-01-23r300g: Increase fragment shader limits for r400 cardsTom Stellard
r400 fragment shaders now support up to 64 temporary registers, 512 ALU instructions, and 512 TEX instructions.
2011-01-23gldirect: remove _NEW_ACCUMBrian Paul
2011-01-23i965: remove _NEW_ACCUMBrian Paul
2011-01-23r300/compiler: remove any code related to relative addressing of temporariesMarek Olšák
The hw can't do it and the code was useless anyway (it's lowered in the GLSL compiler).
2011-01-21glsl, i965: Remove unnecessary talloc includes.Kenneth Graunke
These are already picked up by ir.h or glsl_types.h.
2011-01-21r600c: get OQ results only for 4 DBs on r600 classAndre Maasikas
- since evergreen addition which increased this to 8 depth backends other bytes may contain garbage values
2011-01-20intel: Fix typeos from 3d028024 and 790ff232Ian Romanick
...and remove egg from face.
2011-01-20i915: Set correct values for range/precision of fragment shader typesIan Romanick
2011-01-20i965: Set correct values for range/precision of fragment shader typesIan Romanick
2011-01-20r600c: bump sq gpr resources if a shader needs more than defaultAndre Maasikas
ideally this should be set once in the beginning of CS but there's no way to change values there while in the middle of rendering. For now reemitting SQ setup seems to work probably due to r700WaitForIdleClean after each render currently does not to try to decrease values once increased fixes hangs in glsl-vs-vec4-indexing-temp-src-in-nested-loop-combined glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined for my rv740 maybe more for other chips
2011-01-20glapi: Fix OpenGL and OpenGL ES interop.Chia-I Wu
When --enable-shared-glapi is specified, libGL will share libglapi with OpenGL ES instead of defining its own copy of glapi. This makes sure an app will get only one copy of glapi in its address space. The new option is disabled by default. When enabled, libGL and libglapi must be built from the same source tree and distributed together. This requirement comes from the fact that the dispatch offsets used by these libraries are re-assigned whenever GLAPI XMLs are changed. For GLX, indirect rendering for has_different_protocol() functions is tricky. A has_different_protocol() function is assigned only one dispatch offset, yet each entry point needs a different protocol opcode. It cannot be supported by the shared glapi. The fix to this is to make glXGetProcAddress handle such functions specially before calling _glapi_get_proc_address. Note that these files are automatically generated/re-generated src/glx/indirect.c src/glx/indirect.h src/mapi/glapi/glapi_mapi_tmp.h
2011-01-20r200: fix up some problems with TFP on r200Dave Airlie
2011-01-19i965/fs: Take the shared mathbox into account in instruction scheduling.Eric Anholt
I don't have evidence for this amounting to any improvement, but it does codify a bit more what we understand so far about the pipeline.
2011-01-19i965/fs: Add a helper function for detecting math opcodes.Eric Anholt
2011-01-19i965/fs: Assign URB/CURB register numbers after instruction scheduling.Eric Anholt
This fixes a bunch of unnecessary barriers due to the scheduler not knowing what that arbitrary register description refers to when trying to reason about its dependencies. The result is rescheduling in the convolution kernel shader in Lightsmark, which results in avoiding register spilling and increasing the performance of the first scene from 6-7 fps midway through the panning to 11fps. The register spilling was a regression from Mesa 7.9 to Mesa 7.10.
2011-01-19i965/fs: Add an instruction scheduler.Eric Anholt
Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also reschedules the giant multiply tree at the end of glsl-fs-convolution-1 so that we end up not spilling registers, producing the expected level of performance.
2011-01-19i965/fs: Add a helper for detecting texturing opcodes.Eric Anholt
2011-01-19radeon: avoid segfault on 3D textures.Dave Airlie
This is a candidate for 7.9 and 7.10
2011-01-19radeon: oops didn't need this logbase2 fnDave Airlie
2011-01-19radeon: calculate complete texture state inside TFP functionDave Airlie
(really not sure why I'm doing this). This is a candidate for 7.9 and 7.10 branches.
2011-01-19dri/nouveau: allow multiple maps of surface buffersBen Skeggs
Can happen during swrast fallbacks if a buffer is somehow bound as a render target and a texture. Fixes gnome-shell on nv20, and gets it mostly working on nv10. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-01-19radeon/r200: fix fbo-clearmipmap + gen-teximageDave Airlie
sw clears were being used and not getting the correct offsets in the span code. also not emitting correct offsets for CB draws to texture levels. (I've no idea why I'm playing with r100). This is a candidate for 7.9 and 7.10