| Age | Commit message (Collapse) | Author |
|---|
|
+269 piglits
|
|
It hangs the GPU due to FB_WRITE handling being incomplete. There are
bigger issues to handle first.
|
|
|
|
I'm also fixing this upstream in libdrm, but this avoids new libdrm
dependency for the moment.
|
|
This should make debugging way easier, as now we have context for
reading large programs.
|
|
|
|
At least some tests, like glsl-vs-sign, now work.
|
|
This can successfully emit a real program that generates magenta now.
|
|
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
|
|
Combined with the previous pass, this lets other optimization passes
do their work thanks to ir_tree_grafting. Still have regression in
instruction count with INTEL_NEW_FS, but register count is even
better.
|
|
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
|
|
|
|
Fixes: glsl-vs-varying-array
|
|
Shader inputs appear in source registers, not dst registers. Catches
unsupported shaders in glsl-fs-varying-array and Humus
RaytracedShadows.
|
|
Signed-off-by: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Brian Paul <brianp@vmware.com>
|
|
when we dont know max_index we cannot calculate vb size from count
anymore - just use the bo size.
Also added an assert to remind that we dont handle GL_INT GL_DOUBLE
upload when we dont' know max_index - will fix later
|
|
|
|
|
|
Texcoords in AmbientApertureLighting were getting trashed since the
move of math arguments to implied moves, due to the logic for
detecting ALU message reg writes overriding the logic for SEND
implicit message reg writes.
|
|
3 more piglits, cool.
|
|
|
|
|
|
|
|
Include r600_emit.h for r600EmitShader and r600EmitShaderConsts symbols.
Fixes the following GCC warnings.
evergreen_fragprog.c: In function 'evergreenSetupFragmentProgram':
evergreen_fragprog.c:521: warning: implicit declaration of function 'r600EmitShader'
evergreen_fragprog.c:778: warning: implicit declaration of function 'r600EmitShaderConsts'
|
|
Include r600_emit.h for r600EmitShader and r600EmitShaderConsts symbols.
Fixes the following GCC warnings.
evergreen_vertprog.c:614: warning: implicit declaration of function 'r600EmitShader'
evergreen_vertprog.c:701: warning: implicit declaration of function 'r600EmitShaderConsts'
|
|
The variable loops would be used uninitialized if it ever processed a
RC_OPCODE_ENDLOOP case first.
This patch initalizes the loops variable to NULL and adds an assert at
the RC_OPCODE_ENDLOOP case that loops isn't NULL.
Silence the following GCC warning.
r3xx_vertprog.c: In function 'translate_vertex_program':
r3xx_vertprog.c:469: warning: 'loops' may be used uninitialized in this function
|
|
This is a follow-on patch to commit
574ba4b5f50bfe661427327cd792a8a200559376.
Fixes r300g SCons build.
|
|
Fixes the following GCC warning.
evergreen_render.c: In function 'evergreenTryDrawPrims':
evergreen_render.c:836: error: implicit declaration of function 'evergreenSetupFragmentProgram'
|
|
Silences the following GCC warning.
evergreen_state.c: In function 'evergreenSetBlendState':
evergreen_state.c:341: warning: unused variable 'id'
|
|
|
|
Fixes the following GCC warning.
r600_emit.c In function 'r600AllocShaderConsts':
r600_emit.c:59: warning: unused variable 'out'
|
|
Fixes the following GCC warnings.
r600_cmdbuf.h:201: warning: backslash and newline separated by space
r600_cmdbuf.h:202: warning: backslash and newline separated by space
|
|
Wine likes to create a *lot* of constants, exceeding the size of the constant
file in hw.
|
|
Also rename "compiler" to "c".
|
|
i.e. relative addressing (mainly FS), saturate modifiers, exceeding
the maximum number of constants.
|
|
|
|
If there is relative addressing of temporaries, we cannot change register
indices, so skip register allocation entirely. To utilize register allocation
at least partially, we need separate indexable and non-indexable register
files in both TGSI and Mesa IR.
|
|
glxinfo and glxgears run on swrast and softpipe without undefined symbol
errors.
|
|
The spec specifically sets the minimum MAX_SAMPLES at 1 to allow exposing
the extension on all implementations, so do so.
|
|
|
|
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
|
My merge of Zhenyu's patch on top of my previous patches broke it by
my code expecting simd16 single write and Zhenyu's simd8 path being
disabled by mine. Merge the two for success.
|
|
The docs claim two conflicting things: One, that a scalar source is
supported. Two, source hstride must be 1 and width must be exec size.
So splat a constant argument out into a full reg to operate on, since
violating the second set of constraints is clearly failing.
The alternative here might be to do a 1-wide exec on a constant
argument for math1. It would probably save cycles too. But I'll
leave that for the glsl2-965 branch.
Fixes glsl-algebraic-div-one-2.shader_test.
|
|
Fixes glsl-algebraic-add-add-1.
|
|
|
|
|
|
Only 8 out of the up to 13 regs are for source/dest depth, so the name
wasn't particularly appropriate. Note that this doesn't count the
constant or URB payload regs. Also, don't pre-divide by 2, so it's
actually a number of registers.
|
|
|
|
|
|
|
