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2009-11-21radeon: fix compressed mipmapped texturesMaciej Cencora
Tested on r300 only, other cards may require adjusting texture_compressed_row_align.
2009-11-21radeon: fix glCompressedTexSubImageMaciej Cencora
2009-11-21intel: make CopyTex[Sub]Image fallback debug messages more consistentRoland Scheidegger
2009-11-21i965: Fix several memory leaks on exit.Eric Anholt
Bug #25194.
2009-11-20r100: fix texture_from_pixmap and compiz.Dave Airlie
r100 state emission has separate rect and non-rect states, if we are doing TFP for a TEXTURE_2D we shouldn't use the rect states as they won't get emitted properly. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-18r300: allow disabling s3tc support if libtxc_dxtn is availableMaciej Cencora
2009-11-18Merge branch 'radeon-texrewrite-clean' into mesa_7_7_branchMaciej Cencora
2009-11-18r600: align for mipmap tree changesMaciej Cencora
2009-11-17Merge branch 'outputswritten64'Ian Romanick
Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
2009-11-17r200: align for mipmap tree changesMaciej Cencora
2009-11-17radeon: align for mipmap tree changesMaciej Cencora
2009-11-17r300: fix reads and writes for MESA_FORMAT_S8Z24 bufferMaciej Cencora
Regression was introduced by texformat-rework branch merge.
2009-11-17Remove unconditional use of glibc specific bswap_16() macro.Michel Dänzer
Fixes unresolved symbol bswap_16 on non-glibc or little endian glibc platforms.
2009-11-17dri: Ensure subdirs have finished before linking driverDan Nicholson
Recursive make is hard. If there are subdirectories in the DRI drivers, it's pretty certain we want to finish building in them before linking the driver. Add a new target to serialize the rules. Signed-off-by: Dan Nicholson <dbn.lists@gmail.com>
2009-11-17r600: More span breakage fixes.Michel Dänzer
At least now the compiler doesn't complain about implicitly declared functions anymore...
2009-11-17r600: Attempt to fix span breakage introduced by big endian fixes.Michel Dänzer
Only compile tested; I happened to notice people on IRC reporting .../r600_dri.so: undefined symbol: radeon_ptr_2byte_8x2
2009-11-17radeon: Depth/stencil span code fixes for big endian.Michel Dänzer
Fixes e.g. text in progs/demos/arbocclude.
2009-11-17radeon: Fix occlusion queries on big endian.Michel Dänzer
2009-11-17radeon: Fix software fallbacks with KMS on big endian.Michel Dänzer
2009-11-17radeon: FBO fixes for big endian.Michel Dänzer
2009-11-17radeon: rn50's have no 3D engine so don't try and init 3D driver.Dave Airlie
2009-11-16i965: Use MESA_FORMAT_AL1616 when appropriateIan Romanick
2009-11-16r600: don't force Z orderAlex Deucher
Let the hw decide (early vs late Z) fixes fdo bug 25092 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-11-16mesa: remove unused vertex array driver hooksBrian Paul
2009-11-14radeon: return false on texture validation if texture isn't completeMaciej Cencora
2009-11-14radeon: rework mipmap treeMaciej Cencora
2009-11-14radeon: more texture code refactoringMaciej Cencora
2009-11-14radeon: minor refactoring of texture codeMaciej Cencora
Also properly set dstImageOffsets for TexSubImage case.
2009-11-14radeon: rework mipmap tree reference countingMaciej Cencora
2009-11-14r300: fix regression introduced in 1d5a06a1f7812c055db1d724e40d21a0e3686dd1Maciej Cencora
Spotted by Dave Airlie
2009-11-14radeon: use radeon_bo_is_referenced_by_cs for query objectsMaciej Cencora
2009-11-14radeon/r300: don't flush cmdbuf if not necessaryMaciej Cencora
2009-11-14radeon/r300: no need to flush the cmdbuf when changing scissors state in KMM ↵Maciej Cencora
mode
2009-11-14radeon: fix glBufferSubDataMaciej Cencora
2009-11-14radeon: add radeon_bo_is_referenced_by_cs functionMaciej Cencora
2009-11-14radeon: remove unnecessary call to radeonEmitStateMaciej Cencora
fixes bo space accounting errors
2009-11-14r300: add missing texformatMaciej Cencora
2009-11-14r300: remove unneeded includesMaciej Cencora
2009-11-13i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix TXB on G45 and older in the GLSL case.
2009-11-13i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt
New comments should explain some of the confusion about how this message works.
2009-11-13i965: Clean up emit_tex a bit.Eric Anholt
2009-11-13Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt
2009-11-13i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt
Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965).
2009-11-13intel: Remove some dead context structure fields.Eric Anholt
2009-11-13i965: Remove an unused cache_item field.Eric Anholt
2009-11-13i965: Remove long dead structures for ffvertex_prog.c.Eric Anholt
2009-11-13i965: Use bo_map instead of subdata to upload the bits of constant buffer.Eric Anholt
Saves CPU time, resulting in a 2.5% FPS win on ETQW.
2009-11-13i965: Validate the number of URB entries selected for the VS.Eric Anholt
2009-11-13intel: When subdataing a busy buffer, use a temporary and blit in.Eric Anholt
This cuts a massive number of waits in ET:QW, which uses a VBO ringbuffer. Unfortunately it doesn't BufferData when wrapping back to 0, so we can't be clever with tracking what's been initialized.
2009-11-13i965: Clean up Ironlake sampler type definitions.Eric Anholt
They're the same regardless of execution width for 8, 4x2, and 16.