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CMP may now use two less temps, other non-native instructions may end up
using one less temp, except for SIN/COS/SCS, which I am leaving unchanged
for now.
This may reduce register pressure inside loops, because the register
allocator doesn't do a very good job there.
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This bug can only be triggered if you put deadcode before native rewrite.
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The same check is already in a later pass (translate_vertex_program).
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Fixes glean/blendFunc
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Fixes:
glean/glsl1-! (not) operator (1, fail)
glean/glsl1-! (not) operator (1, pass)
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With the change of extended math from having the arguments moved into
mrfs and handed off through message passing to being directly hooked
up to the EU, it looks like the piece for doing source modifiers
(negate and abs) was left out.
Fixes:
fog-modes
glean/fp1-ARB_fog_exp test
glean/fp1-ARB_fog_exp2 test
glean/fp1-Computed fog exp test
glean/fp1-Computed fog exp2 test
ext_fog_coord-modes
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This can significantly ease thinking about the asm.
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Previously the code only handled scalars and vectors. This new code
is modeled somewhat after similar code in ir_to_mesa.
Reviewed-by: Eric Anholt <eric@anholt.net>
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gen6 builtin RSQ apparently clamps negative values to 0 instead of
returning the RSQ of the absolute value like ARB_fragment_program
desires and pre-gen6 apparently does.
Fixes:
glean/fp1-RSQ test 2 (reciprocal square root of negative value)
glean/vp1-RSQ test 2 (reciprocal square root of negative value)
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We get saturate as an argument to brw_math() instead of as compile
state, since that's how the pre-gen6 send instructions work. Fixes
fp-ex2-sat.
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This is the push constant buffer, not the pull constants.
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Be sure polygon stipple mode is updated. This fixes 'gamma' demo.
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Fixes this GCC warning.
r200_maos_arrays.c: In function 'r200EmitArrays':
r200_maos_arrays.c:113: warning: 'emitsize' may be used uninitialized in this function
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It is used for point width on vertex. This fixes mesa demo spriteblast and pointblast.
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It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
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Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
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The FS backend is fine with register level granularity. But for the
brw_wm_emit.c backend, it expects pairs of regs to be used for the
constants, because the whole world is pairs of regs. If an odd number
got used, we went looking for interpolation in the wrong place.
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We were accidentally doing a float-to-uint conversion.
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We were trying to do the implied move even when we'd already manually
moved the real header in place.
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In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6,
the setup for 16-wide interpolation was left behind. This brings
relative sanity to that path too.
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Fixes many assertion failures in that path.
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Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
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Need to check the required primitive type for GS on Sandybridge,
and when GS is disabled, the new state has to be issued too, instead
of only updating URB state with no GS entry, that caused hang on Sandybridge.
This fixes hang issue during conformance suite testing.
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use constant interpolation instead of linear interpolation for
attributes COL0,COL1 if GL_FLAT is used. This fixes mesa demo bounce.
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SF state depends on what inputs there are to the fragment program, not
just the outputs of the VS.
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Sometimes I'm on the train and want to just read what's generated
under INTEL_DEBUG=vs,wm for some code on another generation. Or, for
the next gen enablement we'll want to dump aub files before we have
the actual hardware. This will let us do that.
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Fixes nasty bug where some parts of the code didn't define WIN32_THREADS
and were using the integer mutex implementation, causing even confusion
to the debuggers.
And there is little interest of other thread implemenation on Win32
besides Win32 threads.
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It was a no-op because all swizzles are native there.
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This fixes some mesa demos such as fslight/engine in wireframe mode.
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This follows the changes done for the FS alongside the EU emit code.
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While the actual IF instructions were fixed by Zhenyu, we were still
flattening them to conditional moves.
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At this point, piglit tests for fragment shader loops are working.
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There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
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There's no more DO since there's no more mask stack, and WHILE has
been shuffled like IF was.
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Fixes piglit test glsl-fs-discard-03.
NOTE: This is a candidate for the 7.9 branch.
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There were a few places where we were using the wrong opcodes
on evergreen. arl still needs to be fixed on evergreen; see
r600g for reference.
NOTE: This is a candidate for the 7.9 branch.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Needed for st/vega.
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Like Eric's workaround patch of commit 490c23ee6be2e8531b5a14d42f808de83d401130.
This forces to align1 mode for math2 too.
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