Age | Commit message (Collapse) | Author |
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This doesn't seem to really effect anything but seeing width=0 in drawing
regions was confusing.
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The i965 driver needs an extra instruction field for color output information.
It was using the Sampler field for this. Use the Aux field instead. This
will probaby be revisited at some point...
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It is possible that an object whose vertices all are outside of a
view plane is passed to clip thread due to the RHW workaround. This
object should be rejected by clip thread. Fix bug #19879
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While it's a nice idea to be able to allow clients to choose a smaller
(or bigger for 16bpp screens!) depth size, right now DRI2 hands back a buffer
with a size that matches the drawable, rather than being based off of the
visual. This led to problems in readback as parts of the driver disagreed
on what format the depth buffer was really in.
Fixes the remainder of bug #19447.
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It seems that in this case the Mesa code is handing us x8z24 values instead
of z24s8 values, so we need to not do the rotation. Fixes half of OGLconform
depthrange.c.
Bug #19447.
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This is insanity, but so is copying the same blocks containing the actual
interesting code in the file three times each for the different tile formats.
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I was lured into a false sense of security by the fact that the spans code was
already there, and a bunch of tests didn't catch the problem. oglconform's
mask.c did, though.
Bug #19970.
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When doing line stipple, the stipple count resets on each line segment,
unless the primitive is a GL_LINE_LOOP or a GL_LINE_STRIP.
The existing code correctly identifies the need for a software fallback
to handle conformant line stipple on GL_LINE_LOOP primitives, but
neglects to make the same assessment on GL_LINE_STRIP primitives.
This fixes it so they match.
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This trims down and cleans up imports.h and glheader.h quite a bit.
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Reported by cjb via tinderbox on irc
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Use loops to consolidate lots of texture object code.
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New gl_texgen struct allows quite a bit of code reduction.
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The intelImage also holds a reference to the miptree, so unref that as well.
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This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
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We were asking for something illegal (write_domain != 0 && read_domains !=
write_domain) because at the time of writing the region surfaces were used
for texturing occasionally as well, and we weren't really clear on the model
GEM was going to use.
This reliably triggered a kernel bug with domain handling, resulting in
oglconform mustpass.c failure. Of course, it only became visible after
01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing.
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GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
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Note that I24X8 vs. A24X8 vs. L24X8 doesn't seem to make any difference
for texture/shadow compare, however.
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Fixes mysterious failures in glean glsl1 test.
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Prints program parameter info
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This is a 2% win in fbo_firecube, and would avoid a sw fallback for
masked clears.
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Noticed this with the fbotexture demo.
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The default for EmitCondCodes got flipped when gallium-0.2 was merged.
This fixes GLSL if/else/endif regressions.
Drivers that use GLSL should always explicitly set the flag to be safe.
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R3xx/R5xx fragment program texture constants must come from a hardware
register instead of the constant file, so we redirect if necessary during
the native rewrite phase.
The symptoms of this bug started appearing when the Mesa fixed function
texenvprogram code started using STATE_CURRENT_ATTRIB constants for
texture coordinates when the corresponding attributes were constant across
all vertices.
Signed-off-by: Nicolai Haehnle <nhaehnle@gmail.com>
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Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
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This doesn't effect correctness, but we were emitting an extraneous ADD.
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It's done in the Mesa GLSL compiler. The only part of it that might
matter in drivers is the centroid sampling option for MSAA.
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While running conform with render-to-texture:
conform -d 33 -v 2 -t -direct
the i965 driver failed this assertion:
intel_clear.c:77: intel_clear_tris: Assertion `(mask & ~((1 << BUFFER_BACK_LEFT) | (1 << BUFFER_FRONT_LEFT) | (1 << BUFFER_DEPTH) | (1 << BUFFER_STENCIL))) == 0' failed.
The problem is that intel_clear_tris() is called by intelClear() to
clear any and all of the available color buffers, but intel_clear_tris()
actually only handles the back left and front left color buffers; so
the assertion fails as soon as you try to clear a non-standard color
buffer.
The fix is to have intelClear() only call intel_clear_tris() with
buffers that intel_clear_tris() can support. intelClear() already backs
down to _swrast_Clear() for all buffers that aren't handled explicitly.
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This involved fixing driConcatConfigs to not return const (which had made a
mess of a previous patch too).
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