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2009-09-16Merge branch 'mesa_7_6_branch'Ian Romanick
2009-09-16Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/main/dlist.c
2009-09-16intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick
The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a context. However, the intel_context structure keeps cached copies of these pointers. If these cached pointers are not NULLed and the drawable is actually destroyed after unbinding the context (typically by way of glXDestroyWindow), freed memory will be dereferenced in intelDestroyContext. This should fix bug #23418.
2009-09-16i965: do a flush in clear, fix openarena render issue,Zou Nan hai
fd.o bug# 23857
2009-09-16radeon: cleanup compile defines mess.Dave Airlie
I inherited this and really it stayed around far too long, make it nice and simple.
2009-09-16radeon: oops remove debugging left on in previous patchDave Airlie
2009-09-16radeon: use txformat to decide to emit rect tex state.Dave Airlie
This is more logical, and fixes a TFP issue.
2009-09-15mesa: move generate mipmap callsBrian Paul
Per the suggestion in the Intel driver, move the calls to ctx->Driver.GenerateMipmap() into core Mesa so that drivers don't have to worry about it.
2009-09-15radeon: don't build non-r600 span code on r600Alex Deucher
2009-09-15r600: minor span cleanupsAlex Deucher
2009-09-15mesa: remove incorrect texture state checkBrian Paul
Fixes incorrectly textured bitmap text in engine demo. It's incorrect to test the texture enable bits here since they may have been changed by disabling the shader above. Optimization is still possible but will have to be reexamined.
2009-09-15Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-15r600: support position_invariant programsAndre Maasikas
2009-09-14r600: add span support for 1D tilesAlex Deucher
1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z*
2009-09-14r600: fix warningAlex Deucher
Noticed by rnoland on IRC.
2009-09-14intel: minor code clean-upsBrian Paul
2009-09-14intel: fix renderbuffer map/unmap regressionBrian Paul
Commit 36dd53a3cded9d003ec418732b7fc93c1476aa9b caused a few regressions because the glReadBuffer() buffer wasn't getting mapped when GL_READ_BUFFER != GL_DRAW_BUFFER.
2009-09-14intel: remove unneeded driver function assignmentsBrian Paul
These default swrast functions are already installed by _mesa_init_driver_functions().
2009-09-11i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt
Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
2009-09-11r600: fix texcoords from constantsAndre Maasikas
with some minor updates from Richard.
2009-09-11Revert "r600: support tex coords from constants"Alex Deucher
This reverts commit 4099bb76148007f9ccb6c86838b2bf37ea42de56. Tex coord src has to be a GPR.
2009-09-11r600: support tex coords from constantsAlex Deucher
Fixes neverball among other things.
2009-09-11r600: enable caching of vertex programsAndre Maasikas
2009-09-10i965: Enable loops in the VS.Eric Anholt
Passes piglit glsl-vs-loop testcase. Bug #20171
2009-09-10mesa: nicer vertex setupBrian Paul
2009-09-11radeon: Remove structure allocation from iterator variable.Pauli Nieminen
dma_bo varaible is only used for iterating so allocating memory for it only causes memory leaks.
2009-09-10Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-10intel: disable intel_stencil_drawpixels() for nowBrian Paul
It doesn't work reliably even when all the prerequisite checks are made.
2009-09-10Fix merge failIan Romanick
One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <brianp@vmware.com> Date: Wed Sep 9 08:33:39 2009 -0600
2009-09-10mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul
Plus, check for pixel transfer stencil index/offset.
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/drivers/dri/intel/intel_context.c
2009-09-10i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
2009-09-10intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
2009-09-10intel: Don't forget to map the depth read buffer in spans.Eric Anholt
This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
2009-09-10r300: enable rb3d_discard_src_pixel_lte_threshold for more chips on dri2Alex Deucher
2009-09-10r300: add full support for two sided stencil on r5xx for dri2Alex Deucher
2009-09-10mesa: fix cut&paste typosMathias Frohlich
2009-09-10radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen
Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
2009-09-09i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254
2009-09-09radeon: Add more verbose error message for failed command buffer.Pauli Nieminen
2009-09-09i965: fix an overlooked merge conflictBrian Paul
2009-09-09r600: check if textures are actually enabled before submissionAlex Deucher
noticed by taiu on IRC.
2009-09-09Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-09mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels()Brian Paul
Works around a bug found on i965. See bug 23670.
2009-09-09r600: fix ftp for dri1Alex Deucher
We use t->bo for dri1 since r600 uses CS for dri1.
2009-09-09intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2009-09-09r600: don't setup hardware state if TFPDave Airlie
if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon
2009-09-08intel: Add support for ARB_draw_elements_base_vertex.Eric Anholt
On the 965, we just drop the value into the primitive packet. On non-945, we rely on the sw tnl code handling it.
2009-09-08mesa: Add support for ARB_draw_elements_base_vertex.Eric Anholt
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