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This uses message headers for now, since we'll need it for MRT. We
can cut out the header later.
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It instead sensibly appears in the src0 slot.
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We could try to detect this in expression handling and do it
proactively there, but it seems like less logic to do it in one
optional pass at the end.
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The glsl core should be handling most dead code issues for us, but we
generate some things in codegen that may not get used, like the 1/w
value or pixel deltas. It seems a lot easier this way than trying to
work out up front whether we're going to use those values or not.
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This also means that our intervals now highlight dead code.
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Easy enough patch, who needs a full test run. Oh, that's right. Me.
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The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't
apply to shadow compares, which always return an intensity value. The
texture swizzles can do the job for us.
Fixes:
glsl1-shadow2D(): 1
glsl1-shadow2D(): 3
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FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
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Luckily, one of them would result in failing out register allocation
when the other bugs were encountered. Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
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This quickly cuts 8% of the instructions in my glsl demo.
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By doing so using the register allocator now, we avoid wasting a
register to make the alignment happen.
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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=30551
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Fixes 36 testcases, including glsl-fs-shadow2d*-bias which fail on the
Mesa IR backend.
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We should fix the SF to actually give us just the data we need, but
this fixes regressions in the new FS until then.
Fixes:
glsl-kwin-blur
glsl-routing
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Fixes glsl1-texcoord varying.
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Since gen5, jumps are in increments of 64 bits instead of increments
of 128-bit instructions.
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Untested, since my hardware is not booting at the moment.
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Trying to track the insanity of the different argument layouts for
normal/shadow crossed with normal/lod/bias one generation at a time is
enough.
Fixes: glsl1-texture2D() with bias.
(first test passing in this code that doesn't pass without it!)
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We should end up with the same code, but anyone else with this issue
could share the handling (which I got wrong for shadow comparisons in
the driver before).
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We'll need a reloc for tiling eventually,
so add it now.
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We were pointing each element at the .x channel of the
ParameterValues.
Fixes glsl1-linear fog.
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We need to walk the type tree to get the right register types for
structure components. Fixes glsl-fs-statevar-call.
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Signed-off-by: Adam Jackson <ajax@redhat.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated includes.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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Larger VBOs avoid many kernel trips to get them in sync with the GPU.
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Sandybridge requires depth buffer must be tiling.
Fix 'fbo_firecube' demo.
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I've screwed this up enough times that I don't think it's worth it.
This time, it was that I was doing it once per top-level body
instruction instead of just once at the end of the loop body.
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Fixes 13 piglit cases that failed at register allocation before.
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The interference is totally bogus (maximal), so this is equivalent to
our trivial register assignment before. As in, passes the same set of
piglit tests.
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Now, virtual GRFs are consecutive integers, rather than offsetting the
next one by the size. We need the size information to still be around
for real register allocation, anyway.
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