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AgeCommit message (Collapse)Author
2009-01-14radeon: get ctx right in copybufferDave Airlie
2009-01-14r200: add missing symbolsDave Airlie
2009-01-14radeon/r200/r300: make legacy emit non-r300 specificDave Airlie
2009-01-14radeon: move debug symbol add DRI2Dave Airlie
2009-01-14r300: start moving new r300 cmdbuf into common codeDave Airlie
2009-01-14radeon/r200/r300: consolidate swap buffersDave Airlie
2009-01-14radeon: remove old lock codeDave Airlie
2009-01-14radeon/r200/r300: consolidate the buffer copy/flip code into one placeDave Airlie
2009-01-14radeon/r200/r300: attempt to move lock to common codeDave Airlie
2009-01-14radeon/r200/r300: initial attempt to convert to common context codeDave Airlie
2009-01-14radeon/r200: move more stuff closer together in contextDave Airlie
2009-01-14radeon/r200: move state atom to common headerDave Airlie
2009-01-13radeon/r200: start splitting out commonalities into separate headersDave Airlie
2009-01-13radeon: use bo_wait to wait for all buffers to be rendered toDave Airlie
Not 100% sure this is correct, but its what Intel does and its better than CP_IDLE.
2009-01-11radeon/r300: add code to setup r300 vs r500 using pci device from kernelDave Airlie
2008-12-22r300: disable settexoffset extension on r300Dave Airlie
2008-12-22radeon: fix library name for consistencyDave Airlie
2008-12-22radeon: remove start/end offset + cleanup some whitespaceDave Airlie
2008-12-22radeon: fixup r500 FP emission for new CSDave Airlie
2008-12-21radeno: hopefully make r200/radeon buildDave Airlie
2008-12-01radeon: make DRI1 one work with new CS mechanismDave Airlie
2008-11-16radeon: cs add print cs callbackJerome Glisse
2008-11-16radeon: fix pointer danglingJerome Glisse
2008-11-15radeon: update to libdrm-radeon API changesJerome Glisse
2008-11-14radeon: dri2 don't forget to free bufferJerome Glisse
2008-11-14r300: release bo from pixmapJerome Glisse
2008-11-14r300: convert to new relocations format (see libdrm-radeon)Jerome Glisse
2008-11-14r300: SetTex extension supportJerome Glisse
2008-11-14r300: cs + DRI2 supportJerome Glisse
If DRI2 is enabled then switch cmd assembly to directly build hw packet.
2008-11-14r300: bo and cs abstraction.Jerome Glisse
This abstract memory management and command stream building so we can use different backend either legacy one which use old pathway or a new one like with a new memory manager. This works was done by : Nicolai Haehnle Dave Airlie Jerome Glisse
2008-11-12i965: Upload state on primitive switch, don't just prepare it.Eric Anholt
This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
2008-11-12i965: Fix VB refcount leak on aperture overflow.Eric Anholt
2008-11-12i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt
As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
2008-11-12i965: Fix up SF max_threads.Eric Anholt
We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
2008-11-12i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt
The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
2008-11-12i965: Update WM maximum threads for G4X.Eric Anholt
2008-11-12i965: Add a big comment explaining my understanding of URB management.Eric Anholt
It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
2008-11-11intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao
This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
2008-11-10mesa: restore glapi/ prefix on #includeBrian Paul
2008-11-10GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul
See bug 18445. When getting array results, __glXReadReply() always reads a multiple of four bytes. This can cause writing to invalid memory when 'n' is not a multiple of four. Special-case the glAreTexturesResident() functions now. To fix the bug, we use a temporary buffer that's a multiple of four bytes in length. NOTE: this commit also reverts part of commit 919ec22ecf72aa163e1b97d8c7381002131ed32c (glx/x11: Added some #ifdef GLX_DIRECT_RENDERING protection) which directly edited the indirect.c file rather than the python generator! I'm not repairing that issue at this time.
2008-11-10dri: alloc __DRIscreen object with calloc()Brian Paul
2008-11-06mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul
Trunc is a more accurate description; there's no type conversion involved.
2008-11-06i965: Always check vertex program.Xiang, Haihao
Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
OPCODE_NOISE4 coming later.
2008-11-02i965: Clean up stale NDC comment.Eric Anholt
2008-11-02i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt
This cuts one MOV out when setting a zero header.
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
2008-11-02i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt
Also, add a comment explaining what brw->urb.constrained tries to do.
2008-11-01Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard
Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com>
2008-10-31intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt
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