| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-08-22 | i965: Use intel->gen >= 6 instead of IS_GEN6. | Eric Anholt | |
| 2010-08-20 | evergreen : initial support driver code. | richard | |
| 2010-08-20 | i965: Rename nr_depth_regs to nr_payload_regs. | Eric Anholt | |
| Only 8 out of the up to 13 regs are for source/dest depth, so the name wasn't particularly appropriate. Note that this doesn't count the constant or URB payload regs. Also, don't pre-divide by 2, so it's actually a number of registers. | |||
| 2010-08-20 | i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB. | Eric Anholt | |
| 2010-08-20 | i965: Add support for FB writes on Sandybridge. | Zhenyu Wang | |
| 2010-08-20 | i965: Set the destination horiz stride even for da16, as SNB seems to need it. | Zhenyu Wang | |
| 2010-08-20 | i965: Set the maximum number of threads on Sandybridge. | Zhenyu Wang | |
| 2010-08-20 | i965: Add AccWrCtl support on Sandybridge. | Zhenyu Wang | |
| Whenever the accumulator results are needed, this bit must be set. | |||
| 2010-08-20 | i965: Mention the mlen and rlen for URB reads. | Zhenyu Wang | |
| 2010-08-20 | i965: Sandybridge doesn't have Compr4 mode, since it's not needed any more. | Zhenyu Wang | |
| 2010-08-20 | i965: Adjust disasm of subreg numbers to be in units of the register type. | Zhenyu Wang | |
| This makes reading the code easier when matching up to the specs, which also use this format. | |||
| 2010-08-20 | i965: Fix DP write channel ordering on Sandybridge. | Eric Anholt | |
| The SIMD16 message no longer has the goofy interleaved format that made Compr4 compression necessary before. | |||
| 2010-08-20 | intel: Don't try to do work for BufferSubData with a size of 0. | Eric Anholt | |
| If we hit the linear blit path, we'd come up with a pitch of 0, then divide by zero. Fixes vbo-subdata-zero, made for bug #28931 (warsow). | |||
| 2010-08-20 | Remove remnants of the old glsl compiler. | Eric Anholt | |
| 2010-08-20 | i965: Fix compile warnings on 64-bit Linux. | Kenneth Graunke | |
| format ‘%d’ expects type ‘int’, but argument 2 has type ‘long int’ | |||
| 2010-08-19 | i915: Remove unnecessary header from i830_context.c. | Vinson Lee | |
| 2010-08-18 | i965: Set the if stack pop count when breaking out of a loop inside an if. | Eric Anholt | |
| Otherwise, we might end up with the if stack pointing at the wrong place. Fixes GPU hang with glsl-vs-if-loop. | |||
| 2010-08-18 | i965: Don't set the swizzle on an immediate value in the VS. | Eric Anholt | |
| Fixes glsl-vs-if-nested (70.0 is not <= 70.000648 thanks to the swizzle bits getting set). Some safety checks are added to make sure this doesn't happen again as we increase the usage of immediate values in program generation. | |||
| 2010-08-18 | glsl2: Free the shader compiler at dri screen destruction. | Eric Anholt | |
| Hooray, we can valgrind again without adding suppressions. This also adds an interface for use by an implementation of glReleaseShaderCompiler(). | |||
| 2010-08-18 | dri2: Clean up the common dri2 options at screen destroy. | Eric Anholt | |
| 2010-08-18 | r600: implement SSG instruction | Andre Maasikas | |
| 2010-08-18 | r600: implement DP2 opcode | Andre Maasikas | |
| 2010-08-17 | i965: Throw a link error when we see a "return" in main(). | Eric Anholt | |
| We'll need to use the HALT instruction to do this right, like returns from other functions. | |||
| 2010-08-17 | i915: Add support for SSG opcode. | Eric Anholt | |
| Fixes glsl-fs-sign and many of the tests of trig builtins. | |||
| 2010-08-17 | i915: Add support for reading output regs in the FS. | Eric Anholt | |
| Fixes glsl-unused-varying and many others, since we produce an output reg read any time gl_FragColor is written inside an if statement. | |||
| 2010-08-17 | i915: Add support for OPCODE_DP2. | Eric Anholt | |
| Fixes glsl-fs-dot-vec2. | |||
| 2010-08-17 | i915: Enable ARB_fragment_shader by default. | Eric Anholt | |
| Now that we have glsl2 with if flattening in place, most shaders will just work. Remaining failing shaders will mostly be due to loop unrolling (in progress), some possible if flattening failures in inlining functions (planning on fixing), and the register/instruction count limits. While the GLSL and GLSL-ES specs say that shaders shouldn't fail to compile/link due to register/instruction limits, in practice we're not the first vendor to expose GLSL on hardware with these limitations. The benefit to application developers of providing a better language for GPU programming is greater than the pain of having to handle instruction limits (which they had to for ARB_fp on this hardware anyway) | |||
| 2010-08-17 | r600c: Handle reads from PROGRAM_OUTPUT | Henri Verbeet | |
| with glsl2, reads from outputs are legal | |||
| 2010-08-17 | i965: Add support for DP2 in the VS. | Eric Anholt | |
| Fixes glsl-vs-dot-vec2. | |||
| 2010-08-17 | r600c: fix dword miscount in blit emit code | Alex Deucher | |
| 2010-08-16 | i965: Use the implied move available in most brw_wm_emit brw_math() calls. | Eric Anholt | |
| This saves an extra message reg move in the program, though I'm not clear on whether it will have any performance impact other than cache footprint. It will also fix those math calls on Sandybridge, where the brw_eu_emit.c brw_math() support relies on the implied move being used. | |||
| 2010-08-16 | i965: Add disasm for Compr4 instruction compression. | Eric Anholt | |
| 2010-08-16 | Merge branch 'glsl2' | Ian Romanick | |
| Conflicts: src/mesa/program/prog_optimize.c | |||
| 2010-08-16 | r600c: blit emit updates | Alex Deucher | |
| - set VGT_MAX_VTX_INDX to a larger value - emit PA_SC_AA_CONFIG. The command checker in 2.6.36+ requires this reg. | |||
| 2010-08-16 | dri/nouveau: test for FEATURE defines | nobled | |
| 'struct dd_function_table' only conditionally contains the function pointer NewFramebuffer and friends based on FEATURE_EXT_framebuffer_* defines. (See src/mesa/main/dd.h) Fixes the build when the features are disabled and the vfuncs don't exist. | |||
| 2010-08-16 | dri/radeon: test for FEATURE defines | nobled | |
| 'struct dd_function_table' only conditionally contains the function pointer NewFramebuffer and friends based on FEATURE_EXT_framebuffer_* defines. (See src/mesa/main/dd.h) Fixes the build when the features are disabled and the vfuncs don't exist. | |||
| 2010-08-16 | r300/compiler: implement DP2 opcode | Marek Olšák | |
| 2010-08-16 | r300/compiler: implement SSG opcode | Marek Olšák | |
| 2010-08-16 | r300/compiler: fix allocation of temporaries in radeonTransformTEX | Marek Olšák | |
| 2010-08-13 | Merge branch 'master' into glsl2 | Ian Romanick | |
| 2010-08-13 | mesa: Avoid using c++ keyword in dri_util.h when compiled with c++. | Eric Anholt | |
| 2010-08-13 | intel: Remove include of texmem.h, since we haven't used it in ages. | Eric Anholt | |
| 2010-08-12 | r600: add support for draw_elements_base_vertex | Andre Maasikas | |
| use VTX_BASE_VTX_LOC for offset, last time using INDEX_OFFSET was probably a wrong register for this | |||
| 2010-08-12 | r300/compiler: remove an unused variable | Marek Olšák | |
| 2010-08-11 | osmesa: link with new libglsl.a lib | Brian Paul | |
| 2010-08-11 | r300/compiler: Implement the CONT opcode. | Tom Stellard | |
| 2010-08-11 | r300/compiler: Handle loops in the register allocator. | Tom Stellard | |
| 2010-08-11 | r300g: implement gl_FrontFacing | Marek Olšák | |
| 2010-08-10 | r300/compiler: Use predicate bit for IF statements in r500 vertex shaders | Tom Stellard | |
| 2010-08-10 | r300/compiler: Implement hardware assisted loops for vertex shaders. | Tom Stellard | |
| Single loops work, but nested loops do not. | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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