Age | Commit message (Collapse) | Author |
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Each array element is now a BUFFER_x token rather than a BUFFER_BIT_x bitmask.
The number of active color buffers is specified by _NumColorDrawBuffers.
This builds on the previous DrawBuffer changes and will help with drivers
implementing GL_ARB_draw_buffers.
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These fields are no longer indexed by shader output. Now, we just have
a simple array of renderbuffer pointers.
If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.
A few more changes and simplifications can follow from this...
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rendering. fix #12786
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By avoiding the repeated relocation buffer creation/map/unmap/destroy for each
new batch buffer, this improves OpenArena framerates by 30%. Caching batch
buffers themselves doesn't appear to be a significant performance win over
this change.
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We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
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MRD computation is now changed in mesa core
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This reverts commit 8bb9ae3693362a302206255c61f512d942df9bbf.
Validating our kernel buffers with the caching off in flags but on in mask
means that the kernel migrates the buffer to be uncached, which is undesired.
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The 'mask' value used in the validation operation specifies which of the
'flags' bits are being modified. Buffer validation wants to pass the memory
type and access mode (rwx) to the kernel so that the buffer will be placed
correctly, and so that the right kind of fence will be created (read vs
write). That means we actually want a constant mask for these operations,
and not something computed from the bits coming in. The constant we want is
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE.
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Without this, the WM binding tables would all collide, for example. Improves
openarena performance by around 2%.
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this is correct, there is another issue with sw fallbacks
This reverts commit cc50edbca2fd3111f9987d4117fa6656599d79dc.
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I've no idea why I added this so I'll have to spend time tracking it down
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In order to optimize DrawPixels, the i915 texenv program isn't
applied to swrast DrawPixels in the i915 driver. This causes this
program isn't applied to any following swrast functions. Resetting
the swrast state fixes this issue. Fix #13614
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fix #11925
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This fixes 3D rendering on x700 SE chips. Reported
by Kano.
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primitive needs to include the begin/end flags (broken since vbo-0.2). Should
fix missing first/last line segment on gamma, i810, i915, mga, r200, radeon,
s3v, savage, unichrome (r300 already correct). Tested on r200, fixes #13527.
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Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed
_TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to
GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
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To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
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The core problem was that _mesa_generate_mipmap was not respecting RowStride
of the source image. Additionally, the intel private data associated with the
images (level and face) was not being initialized for the
_mesa_generate_mipmap-generated images.
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The 965 driver relies on flag checking instead of these hooks, and will be
using this code soon.
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Otherwise, we may violate cliprect asssertions on clearing the buffers, which
isn't affected by the fallback.
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it ensures there are sufficient registers for all subroutines.
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GS thread. fix #13240
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Fixes a crash when buffer objects are left around until context destroy.
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This fixes a crash when stippling using data from a PBO.
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The diffuse color format is always ARGB32, regardless of the destination
surface format.
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mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
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