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2011-01-07intel: Make renderbuffer tiling choice match texture tiling choice.Eric Anholt
There really shouldn't be any difference between the two for us. Fixes a bug where Z16 renderbuffers would be untiled on gen6, likely leading to hangs.
2011-01-07intel: Use the _BaseFormat from MESA_FORMAT_* in renderbuffer setup.Eric Anholt
2011-01-07i915: Drop old checks for the settexoffset hack.Eric Anholt
2011-01-07i915: Don't claim to support AL1616 when neither 830 nor 915 does it.Eric Anholt
Fixes an abort in fbo-generatemipmap-formats.
2011-01-07intel: Add a vtbl hook for determining if a format is renderable.Eric Anholt
By relying on just intel_span_supports_format, some formats that aren't supported pre-gen4 were not reporting FBO incomplete. And we also complained in stderr when it happened on i915 because draw_region gets called before framebuffer completeness validation.
2011-01-07intel: expose ARB_framebuffer_object in the i915 driver.Eric Anholt
ARB_fbo no longer disallows mismatched width/height on attachments (shouldn't be any problem), mixed format color attachments (we only support 1), and L/A/LA/I color attachments (we already reject them on 965 too). It requires Gen'ed names (driver doesn't care), and adds FramebufferTextureLayer (we don't do texture arrays). So it looks like we're already in the position we need to be for this extension. Bug #27468, #32381.
2011-01-07i965: Avoid double-negation of immediate values in the VS.Eric Anholt
In general, we have to negate in immediate values we pass in because the src1 negate field in the register description is in the bits3 slot that the 32-bit value is loaded into, so it's ignored by the hardware. However, the src0 negate field is in bits1, so after we'd negated the immediate value loaded in, it would also get negated through the register description. This broke this VP instruction in the position calculation in civ4: MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y; Bug #30156
2011-01-07r600c: fix up SQ setup in blit code for Ontario/NIAlex Deucher
2011-01-06r600c: add support for NI asicsAlex Deucher
2011-01-06i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke
This should make it easier to cross-reference the code and hardware documentation, as well as clear up any confusion on whether constants like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+). This does not rename any pre-gen6 defines.
2011-01-06mesa: fix build for NetBSDPierre Allegraud
See http://bugs.freedesktop.org/show_bug.cgi?id=32859 NOTE: This is a candidate for the 7.9 and 7.10 branches. Signed-off-by: Brian Paul <brianp@vmware.com>
2011-01-06i965: skip too small size mipmapZou Nan hai
this fixes doom3 crash.
2011-01-05i915: Fix build for previous commit.Eric Anholt
2011-01-05intel: Always allocate miptrees from level 0, not tObj->BaseLevel.Eric Anholt
BaseLevel/MaxLevel are mostly used for two things: clamping texture access for FBO rendering, and limiting the used mipmap levels when incrementally loading textures. By restricting our mipmap trees to just the current BaseLevel/MaxLevel, we caused reallocation thrashing in the common case, for a theoretical win if someone really did want just levels 2..4 or whatever of their texture object. Bug #30366
2011-01-05intel: Drop unused first/lastlevel args to miptree_create_for_region.Eric Anholt
We're always making a single-level, 0-baselevel miptree.
2011-01-05intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.Eric Anholt
This has always been ugly about our texture code -- object base/max level vs intel object first/last level vs image level vs miptree first/last level. We now get rid of intelObj->first_level which is just tObj->BaseLevel, and make intelObj->_MaxLevel clearly based off of tObj->_MaxLevel instead of duplicating its code (incorrectly, as image->MaxLog2 only considers width/height and not depth!)
2011-01-05i915: Enable LOD preclamping on 8xx like on 915/965.Eric Anholt
Fixes lodclamp-between and lodclamp-between-max.
2011-01-05i915: Implement min/max lod clamping in hardware on 8xx.Eric Anholt
This avoids 8xx-specific texture relayout for min/max lod changes. One step closer to avoiding relayout for base/maxlevel changes!
2011-01-05intel: Drop TEXTURE_RECTANGLE check in miptree layout setup.Eric Anholt
It's already handled by our non-mipmapped MinFilter, since TEXTURE_RECTANGLE is always NEAREST or LINEAR.
2011-01-05intel: Clean up redundant setup of firstLevel.Eric Anholt
It's always BaseLevel (since TEXTURE_RECTANGLE's baselevel can't be changed from 0), except for 8xx minlod hilarity.
2011-01-05intel: Drop a check for GL_TEXTURE_4D_SGIS.Eric Anholt
The SGIS_texture4D extension was thankfully never completed, so we couldn't implement it if we wanted to.
2011-01-05i965: Simplify the renderbuffer setup code.Eric Anholt
It was quite a mess by trying to do NULL renderbuffers and real renderbuffers in the same function. This clarifies the common case of real renderbuffers.
2011-01-05i965: use BLT to clear buffer if possible on SandybridgeXiang, Haihao
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32713
2011-01-04i965: Add support for SRGB DXT1 formats.Eric Anholt
This makes fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc match fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't unpack and repack someone's textures into uncompressed SARGB8 format.
2011-01-04intel: Merge our choosetexformat fallbacks into core.Eric Anholt
We now share the type/format -> MESA_FORMAT_* mappings with software mesa, and the core supports most of the fallbacks hardware drivers will want.
2011-01-04r300/compiler: disable the rename_regs pass for loopsMarek Olšák
This workaround fixes rendering of kwin thumbnails. NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-01-04r300/compiler: Fix black terrain in Civ4Tom Stellard
rc_inst_can_use_presub() wasn't checking for too many RGB sources in Alpha instructions or too many Alpha sources in RGB instructions. Note: This is a candidate for the 7.10 branch.
2011-01-04intel: When validating an FBO's combined depth/stencil, use the given FBO.Eric Anholt
We were looking at the current draw buffer instead to see whether the depth/stencil combination matched. So you'd get told your framebuffer was complete, until you bound it and went to draw and we decided that it was incomplete.
2011-01-04intel: Fix segfaults from trying to use _ColorDrawBuffers in FBO validation.Eric Anholt
The _ColorDrawBuffers is a piece of computed state that gets for the current draw/read buffers at _mesa_update_state time. However, this function actually gets used for non-current draw/read buffers when checking if an FBO is complete from the driver's perspective. So, instead of trying to just look at the attachment points that are currently referenced by glDrawBuffers, look at all attachment points to see if they're driver-supported formats. This appears to actually be more in line with the intent of the spec, too. Fixes a segfault in my upcoming fbo-clear-formats piglit test, and hopefully bug #30278
2011-01-04osmesa: pass context to _mesa_update_framebuffer_visual()Brian Paul
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=32814
2011-01-04i965: Use last vertex convention for quad provoking vertex on sandybridgeZhenyu Wang
Until we know how hw converts quads to polygon in beginning of 3D pipeline, for now unconditionally use last vertex convention. Fix glean/clipFlat case.
2011-01-04i965: Correct comment for gen6 fb write control message settingZhenyu Wang
Remove incorrect headless comment for gen6 fb write message. Note current SIMD16 mode has already done right for control message.
2011-01-04i965: Fix provoking vertex select in clip state for sandybridgeZhenyu Wang
Triangle fan provoking vertex for first convention should be 'vertex 1' in sandybridge clip state. Partly fix glean/clipFlat case
2011-01-03intel: Use tri clears when we don't know how to blit clear the format.Eric Anholt
Bug #32207. Fixes ARB_texture_rg/fbo-clear-formats (see my fbo-clear-formats piglit branch currently)
2011-01-03intel: Handle forced swrast clears before other clear bits.Eric Anholt
Fixes a potential segfault on a non-native depthbuffer, and possible accidental swrast fallback on extra color buffers.
2011-01-03radeon: fix build on non-KMS systems.Dave Airlie
Reported on irc by adamk.
2010-12-28i965: Do lowering of array indexing of a vector in the FS.Eric Anholt
Fixes a regression in ember since switching to the native FS backend, and the new piglit tests glsl-fs-vec4-indexing-{2,3} for catching this.
2010-12-28i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.Eric Anholt
Fixes 26 piglit cases on my GM965.
2010-12-28i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.Eric Anholt
2010-12-28i965: Fix occlusion query on sandybridgeZhenyu Wang
Clear target query buffer fixed occlusion query on sandybridge. https://bugs.freedesktop.org/show_bug.cgi?id=32167
2010-12-28Revert "i965: upload multisample state for fragment program change"Zhenyu Wang
This reverts commit de6fd527a545f8344e074312544517d05573fb72. Revert this workaround as it seems the real trouble is caused by lineloop, which doesn't require GS convert on sandybridge actually.
2010-12-27i965: Internally enable GL_NV_blend_square on ES2.Kenneth Graunke
Hopefully should fix bug #32520.
2010-12-27i965: don't spawn GS thread for LINELOOP on SandybridgeXiang, Haihao
LINELOOP is converted to LINESTRIP at the beginning of the 3D pipeline. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32596
2010-12-27i965: Flatten if-statements beyond depth 16 on pre-gen6.Kenneth Graunke
Gen4 and Gen5 hardware can have a maximum supported nesting depth of 16. Previously, shaders with control flow nested 17 levels deep would cause a driver assertion or segmentation fault. Gen6 (Sandybridge) hardware no longer has this restriction. Fixes fd.o bug #31967.
2010-12-25intel: Only do frame throttling at glFlush time when using frontbuffer.Eric Anholt
This is the hack for input interactivity of frontbuffer rendering (like we do for backbuffer at intelDRI2Flush()) by waiting for the n-2 frame to complete before starting a new one. However, for an application doing multiple contexts or regular rebinding of a single context, this would end up lockstepping the CPU to the GPU because every unbind was considered the end of a frame. Improves WOW performance on my Ironlake by 48.8% (+/- 2.3%, n=5)
2010-12-24i965: use align1 access mode for instructions with execSize=1 in VSXiang, Haihao
All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c in oglconform.
2010-12-24i965: fix register region descriptionXiang, Haihao
This fixes brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed.
2010-12-23intel: Remove unnecessary headers.Vinson Lee
2010-12-23i965: Remove unnecessary headers.Vinson Lee
2010-12-23i965: Keep around a copy of the VS constant surface dumping code.Eric Anholt
Just like everywhere else, I never trust my constant uploads to correctly put constants in the right places, even though that's so rarely where the issue is.
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