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path: root/src/mesa/drivers
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2011-03-11mesa: replace NEED_SECONDARY_COLOR(), RGBA_LOGICOP_ENABLED() with inlinesBrian Paul
and rename them.
2011-03-09intel: Don't complain when getparam fails due to a missing param.Eric Anholt
This is an expected behavior when we're testing for the presence of new kernel features.
2011-03-09i965: Pack the tracked state atoms into separate arrays for prepare/emit.Chris Wilson
Improves performance of a hacked-up scissor-many (to reuse a small set of scissors instead of blowing out the cache, and then to run 100x more iterations so it actually took some time) by 3.6% +/- 1.2% (n=10)
2011-03-08r300/compiler: remove unused variablesMarek Olšák
2011-03-08r300/compiler: fix equal and notequal shadow compare functionsMarek Olšák
2011-03-08r300/compiler: detect constants harderMarek Olšák
2011-03-08r300/compiler: improve the detection of constants for constant foldingMarek Olšák
Now the expression V==0 generates one instruction instead of two.
2011-03-08r300/compiler: saturate Z before the shadow comparisonMarek Olšák
This fixes: https://bugs.freedesktop.org/show_bug.cgi?id=31159 NOTE: This is a candidate for the 7.9 and 7.10 branches.
2011-03-07i915: Only invert wpos when rendering to the system framebuffer.Henri Verbeet
2011-03-07i915: Derive the gl_fragment_program from i915_fragment_program.Henri Verbeet
Instead of using the current gl_fragment_program. These aren't necessarily the same, for example when translate_program() is called by i915ValidateFragmentProgram().
2011-03-07intel: check for miptree allocation failureChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-07intel: Add some defense against buffer allocation failure for subimage blitsChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-07intel: Add some defense against bo allocation failureChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-06glx/dri: add initial dri interface for GLX_EXT_framebuffer_sRGB.Dave Airlie
This realigns the name of the glx bit to align with the core mesa names.
2011-03-04i965: Apply a workaround for the Ironlake "vertex flashing".Eric Anholt
This is an awful hack and will hurt performance on Ironlake, but we're at a loss as to what's going wrong otherwise. This is the only common variable we've found that avoids the problem on 4 applications (CelShading, gnome-shell, Pill Popper, and my GLSL demo), while other variables we've tried appear to only be confounding. Neither the specifications nor the hardware team have been able to provide any enlightenment, despite much searching. https://bugs.freedesktop.org/show_bug.cgi?id=29172 Tested by: Chris Lord <chris@linux.intel.com> (Pill Popper) Tested by: Ryan Lortie <desrt@desrt.ca> (gnome-shell)
2011-03-04i965: Fix extending VB packetsChris Wilson
Computation of the delta of this array from the last had a silly little bug and ignored any initial delta==0 causing grief in Nexuiz and friends. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Handle URB_FENCE erratum for BroadwaterChris Wilson
There is a silicon bug which causes unpredictable behaviour if the URB_FENCE command should cross a cache-line boundary. Pad before the command to avoid such occurrences. As this command only applies to gen4/5, do the fixup unconditionally as the specs do not actually state for which chip it was fixed (and the cost is negligible)... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Align index to type size and flush if the type changesChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04intel: Add couple of missing gen6 commands to decodeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Prevent using a zero sized (or of unknown type) vertex arrayChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-03i965: SNB GT1 has only 32k urb and max 128 urb entries.Zou Nan hai
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-03-02i965: Maxinum the usage of urb space on SNB.Zou Nan hai
SNB has 64k urb space, we only use piece of them. The more urb space we alloc, the more concurrent vs threads we can run. push the urb space usage to the limit. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-03-01intel: Support glCopyTexImage() from ARGB8888 to XRGB8888.Kenneth Graunke
Nexuiz was hitting a software fallback.
2011-03-01i965: Use negative relocation deltas to minimse vertex uploadsChris Wilson
With relaxed relocation checking in the kernel, we can specify a negative delta (i.e. pointing outside of the target bo) in order to fake a range in a large buffer. We only then need to upload the elements used and adjust the buffer offset such that they correspond with the indices used in the DrawArrays. (Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01i965: Undo 'continuation of vb packets'Chris Wilson
This breaks nexuiz for unknown reason; disable until a true fix can be found.
2011-03-01i965: Fix uploading of shortened vertex packetsChris Wilson
... handle all cases and not just the interleaved upload. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01i965: Upload all vertices usedChris Wilson
... and take advantage of start_vertex_bias to trim to [min_index, max_index] where possible (i.e. when we need to upload all arrays). Fixes half_float_vertex(misc.fillmode.wireframe) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34595 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01Revert "i965/fs: Correctly set up gl_FragCoord.w on Sandybridge."Kenneth Graunke
This reverts commit 4a3b28113c3d23ba21bb8b8f5ebab7c567083a6d, as it caused a regression on Ironlake (bug #34646).
2011-03-01i965: bump VS thread number to 60 on SNBZou Nan hai
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-02-28mesa: move PBO-related functions into a new fileBrian Paul
2011-02-26intel: Use the current context rather than last bound context for a drawable.Eric Anholt
If another thread bound a context to the drawable then unbound it, the driContextPriv would end up NULL. With the previous two fixes, this fixes glx-multithread-makecurrent-2, despite the issue not being about the multithreaded makecurrent.
2011-02-25i965/fs: Initial plumbing to support TXD.Kenneth Graunke
This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
2011-02-25i965/fs: Complete TXL support on gen5+.Kenneth Graunke
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
2011-02-25i965/fs: Complete TXL support on gen4.Kenneth Graunke
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
2011-02-25i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke
The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're doing a non-bias texture lookup. It has the same value as the new constant BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no functional changes.
2011-02-25i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke
From volume 4, page 161 of the public i965 documentation.
2011-02-24i965: Increase Sandybridge point size clamp in the clip state.Kenneth Graunke
255.875 matches the hardware documentation. Presumably this was a typo. NOTE: This is a candidate for the 7.10 branch, along with commit 2bfc23fb86964e4153f57f2a56248760f6066033. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-24intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebufferNeil Roberts
In the case where glBlitFramebuffer is being used to copy to a texture without scaling it is faster if we can use the hardware to do a blit rather than having to do a texture render. In most of the drivers glCopyTexSubImage2D will use a blit so this patch makes it check for when glBlitFramebuffer is doing a simple copy and then divert to glCopyTexSubImage2D. This was originally proposed as an extension to the common meta-ops. However, it was rejected as using the BLT is only advantageous for Intel hardware. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24i965: Remember to pack the constant blend color as floats into the batchChris Wilson
Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24intel: Reset the buffer offset after releasing reference to packed uploadChris Wilson
Fixes oglc/vbo(basic.bufferdata) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24i965: Unmap the correct pointer after discontiguous uploadChris Wilson
Fixes piglit/fbo-depth-sample-compare: ==14722== Invalid free() / delete / delete[] ==14722== at 0x4C240FD: free (vg_replace_malloc.c:366) ==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd ==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236) ==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24intel: Protect against waiting on a NULL render target boChris Wilson
If we fall back to software rendering due to the render target being absent (GPU hang or other error in creating the named target), then we do not need to nor should we wait upon the results. Reported-by: Magnus Kessler <Magnus.Kessler@gmx.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-23intel: gen3 is particular sensitive to batch sizeChris Wilson
... and prefers a small batch whereas gen4+ prefer a large batch to carry more state. Tuning using openarena/padman indicate that a batch size of just 4096 is best for those cases. Bugzilla: https://bugs.freedesktop.org/process_bug.cgi Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-23i915: And remember assign the new value to the state reg...Chris Wilson
Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22xlib: pass Display pointer to XMesaGarbageCollect()Andy Skinner
Fixes an issue when different displays are used on different threads. Signed-off-by: Brian Paul <brianp@vmware.com>
2011-02-22i965: Increase Sandybridge point size clamp.Kenneth Graunke
255.875 matches the hardware documentation. Presumably this was a typo. Found by inspection. Not known to fix any issues. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke
pixel_w is the final result; wpos_w is used on gen4 to compute it. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Refactor control flow stack handling.Kenneth Graunke
We can't safely use fixed size arrays since Gen6+ supports unlimited nesting of control flow. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke
The code that generates MATH instructions attempts to work around the hardware ignoring source modifiers (abs and negate) by emitting moves into temporaries. Unfortunately, this pass coalesced those registers, restoring the original problem. Avoid doing that. Fixes several OpenGL ES2 conformance failures on Sandybridge. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke
Single-operand math already had these workarounds, but POW (the only two operand function) did not. It needs them too - otherwise we can hit assertion failures in brw_eu_emit.c when code is actually generated. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
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