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This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
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The ARL value is increments of vec4 in the register file. But
PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved
between the two verts being executed (thus a vec8 each), compared to
PROGRAM_STATE_VAR being packed vec4s.
Fixes:
glsl-vs-arrays-2
glsl-vs-mov-after-deref
(without regressing glsl-vs-arrays-3)
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The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
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Otherwise, the second half isn't written, and we end up reading back
black.
Fixes the remaining junk drawn in glsl-max-varyings, and will likely
help with a number of large real-world shaders.
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They go into the render cache, so while we don't care about their
contents after execution, failing to note them could cause the writes
to be flushed over important buffer contents later.
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Otherwise, the subsequent read may not get the written value.
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To quiet a compiler warning.
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When defining mipmap level 'L' and level L-1 exists and the new level's
internalFormat matches level L-1's internalFormat, then use the same hw
format. Otherwise, do the regular ctx->Driver.ChooseTextureFormat() call.
This avoids a problem where we end up choosing different hw formats for
different mipmap levels depending on how the levels are defined (glTexImage
vs. glCopyTexImage vs. glGenerateMipmap, etc).
The root problem is the ChooseTextureFormat() implementation in some
drivers uses the user's glTexImage format/type parameters in the choosing
heuristic. Later mipmap levels might be generated with different calls
(ex: glCopyTexImage()) so we don't always have format/type info and the
driver may choose a different format.
For more background info see the July 2010 mesa-dev thread "Bug in
_mesa_meta_GenerateMipmap"
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The extension never worked, the implementation returns GLX_BAD_CONTEXT
when enabling the frame tracking.
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Only r200 implemented it.
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There was confusion on both the size of message we can send, and on
what the URB destination offset means.
The remaining problems appear to be due to spilling of regs in the
fragment shader being broken.
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This cleans up some chipset dependency sprinkled around, and fixes a
potential overflow of the attribute offset array for many vertex
results.
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Noticed by Henri Verbeet on IRC.
NOTE: This is a candidate for the 7.8 branch.
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This avoids calling radeonFlush() during context destruction, when
ctx->DrawBuffer would be NULL.
NOTE: This is a candidate for the 7.8 branch.
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fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28771
NOTE: This is a candidate for the 7.8 branch.
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Despite the docs, the corresponding hardware instructions are r5xx-only.
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Fix r600_context.h -> r700_oglprog.h -> r600_context.h include
recursion.
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Need to flush command stream before mapping texture image
that is referenced by current cs.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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When searching for valid miptree check images in range
of [BaseLeve, MaxLevel] not [MinLod, MaxLoad].
Prevents unnecessary miptree allocations in cases when during
every rendering operation different texture image level
was selected using MIN_LOD = MAX_LOD = level (for every level
new miptree for whole texture was allocated).
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Always store selected miptree in texObj->mt so get_base_teximage_offset returns correct data.
Found with piglit/mipmap-setup.
Candidate for 7.8 branch.
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Candidate for 7.8 branch
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Fix GCC 'implicit declaration of function' compiler warnings resulting
from commit 00fb58ed5d7104e675fe48d84e5049e5f7dbb9d7.
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Fixes r600_emit.h -> r600_cmdbuf.h -> r600_emit.h include recursion.
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r700_chip.h included r600_context.h, which included r700_chip.h.
Remove the unnecessary r600_context.h inclusion and add missing
headers.
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The other similar integer/float conversion macros are in macros.h.
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This pass renames register in order to make it easier for the pair
scheduler to group TEX instructions together.
This fixes fdo bug #28606
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The following instruction sequence will no longer be emitted in separate
TEX blocks:
0: TEX temp[0].xyz, temp[1].xy__, 2D[0];
1: TEX temp[1].xyz, temp[2].xy__, 2D[0];
This fixes fdo bug #25109
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When EU executes 'wait' instruction, it stalls and sets notification
register state. Host can issue MMIO write to clear notification
register state to allow EU continue on executing again.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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This came from commit cf255e382d147fe3ca450f0dcec3525190e7dcbc
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