| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-12-05 | Don't Swap buffer if a DRIDrawable is entirely obscured | Xiang, Haihao | |
| by another window. | |||
| 2007-12-03 | [965] Change constant buffer from state structs to plain batch emission. | Eric Anholt | |
| Reduces diff to branch which has a relocation in this state emit. | |||
| 2007-12-03 | i915: Fix up state changes for i8xx. | Michel Dänzer | |
| 2007-11-30 | [intel] Move batch bo_unmap from TTM code to shared, and add more asserts. | Eric Anholt | |
| 2007-11-30 | [intel] Add failure path printfs to relocation code and some comments. | Eric Anholt | |
| 2007-11-30 | [intel] Simplify TTM relocation code by passing around bufmgr struct. | Eric Anholt | |
| 2007-11-30 | [intel] Fix the type and naming of the flags/mask args to TTM functions. | Eric Anholt | |
| The uint64_t flags (as defined by drm.h) were being used as unsigned ints in many places. | |||
| 2007-11-30 | [intel] intel_bufmgr_ttm style sanity | Eric Anholt | |
| 2007-11-30 | Merge branch 'master' of git+ssh://joukj@git.freedesktop.org/git/mesa/mesa | joukj | |
| 2007-11-30 | i965: if source depth to render target is set, | Xiang, Haihao | |
| it should be handled in fb_write. | |||
| 2007-11-30 | i965: use uncompressed instruction to ensure only | Xiang, Haihao | |
| Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions. | |||
| 2007-11-29 | [i915] Make INTEL_DEBUG=bufmgr actually do things for bufmgr_fake. | Eric Anholt | |
| 2007-11-29 | New ctx->Driver.Map/UnmapTexture() functions for accessing textures from ↵ | Brian | |
| t_vb_program.c | |||
| 2007-11-28 | r200: Fix texture format regression on big endian systems. | Michel Dänzer | |
| See https://bugs.freedesktop.org/show_bug.cgi?id=13324 . Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets called for MESA_FORMAT_RGB888. | |||
| 2007-11-28 | i965: update RefCount when using Vertex/Fragment program. | Xiang, Haihao | |
| It makes quake4-demo works well on 965. | |||
| 2007-11-27 | use DEFAULT_SOFTWARE_DEPTH_BITS | Delle | |
| 2007-11-27 | i965: The jump instruction count is added | Xiang, Haihao | |
| to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code | |||
| 2007-11-26 | i915: Catch cases where not all state is emitted for a new batchbuffer. | Keith Whitwell | |
| This could lead to incorrect rendering or even lockups. | |||
| 2007-11-26 | i915: Some additional blit fixes and assertions. | Michel Dänzer | |
| 2007-11-25 | intel: Fix relative symlinks. | Michel Dänzer | |
| 2007-11-22 | fix z buffer read/write issue with rv100-like chips and old ddx | Roland Scheidegger | |
| 2007-11-20 | [965] Replace 965 texture format code with common code. | Eric Anholt | |
| The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp. | |||
| 2007-11-20 | [965] Remove dead exec vfmt code which was replaced by generic vbo code. | Eric Anholt | |
| 2007-11-19 | [965] Add INTEL_DEBUG=fall debugging output. | Eric Anholt | |
| 2007-11-19 | [965] Convert DBG macro to use FILE_DEBUG_FLAG like i915. | Eric Anholt | |
| 2007-11-16 | [intel] Add 965 support to shared intel_blit.c | Eric Anholt | |
| This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine. | |||
| 2007-11-16 | [i915] Pass static region names in so debugging says more than "static region". | Eric Anholt | |
| 2007-11-16 | [intel] Move additional code to be shared from intel_context.h to intel/. | Eric Anholt | |
| 2007-11-16 | [intel] Move intel_tex.h into place, forgotten in the previous commit. | Eric Anholt | |
| 2007-11-16 | [965] Add batchbuffer decode for several more packets. | Eric Anholt | |
| 2007-11-16 | [intel] Fix typos in intel_chipset.h macros. | Eric Anholt | |
| 2007-11-16 | [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them. | Eric Anholt | |
| 2007-11-16 | [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat. | Eric Anholt | |
| 2007-11-16 | [intel] Add some doxygen notes on what the bufmgr_fake block members mean. | Eric Anholt | |
| 2007-11-16 | [intel] Add a simple relocation cache to the fake buffer manager. | Eric Anholt | |
| This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them. | |||
| 2007-11-16 | [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c. | Eric Anholt | |
| They shouldn't be created, and this often helps catch stupid issues. | |||
| 2007-11-16 | [intel] Add support for multiple levels of relocation in bufmgr_fake. | Eric Anholt | |
| This is required for 965 support, which has relocations in other places than just the batchbuffer. | |||
| 2007-11-16 | [i915] Push locking in intelClearWithTris down inside meta_draw_poly. | Eric Anholt | |
| The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad. | |||
| 2007-11-15 | fix bogus assumption if ddx has set up surface reg for z buffer | Roland Scheidegger | |
| this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips. | |||
| 2007-11-12 | i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730 | Xiang, Haihao | |
| 2007-11-09 | [i915] Remove old frontbuffer rotation hack. | Eric Anholt | |
| This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately. | |||
| 2007-11-09 | [intel] By default, output batchbuffer decode to stderr like other debug info. | Eric Anholt | |
| 2007-11-09 | [intel] Initialize a depth buffer if the visual has depth 24 but no stencil. | Eric Anholt | |
| 2007-11-09 | [intel] Move over files that will be shared with 965-fbo work. | Eric Anholt | |
| 2007-11-09 | code clean-ups, reformatting | Benno Schulenberg | |
| 2007-11-09 | recreate from changed gl_API.xml | Roland Scheidegger | |
| 2007-11-08 | fix Unichrome/Blender crash, bug 13142 | Benno Schulenberg | |
| 2007-11-06 | r200: Re-expose SetTexOffset functionality. | Michel Dänzer | |
| This seems to have been mismerged with the DRI interface changes. | |||
| 2007-11-06 | r200: Fix SetTexOffset format for 16 bit pixmaps/textures. | Michel Dänzer | |
| Use symbolic array indices to clarify. | |||
| 2007-11-05 | Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL. | Oliver McFadden | |
 |
index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
| summaryrefslogtreecommitdiff |