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2007-11-27use DEFAULT_SOFTWARE_DEPTH_BITSDelle
2007-11-27i965: The jump instruction count is addedXiang, Haihao
to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code
2007-11-26i915: Catch cases where not all state is emitted for a new batchbuffer.Keith Whitwell
This could lead to incorrect rendering or even lockups.
2007-11-26i915: Some additional blit fixes and assertions.Michel Dänzer
2007-11-25intel: Fix relative symlinks.Michel Dänzer
2007-11-22fix z buffer read/write issue with rv100-like chips and old ddxRoland Scheidegger
2007-11-20[965] Replace 965 texture format code with common code.Eric Anholt
The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
2007-11-20[965] Remove dead exec vfmt code which was replaced by generic vbo code.Eric Anholt
2007-11-19[965] Add INTEL_DEBUG=fall debugging output.Eric Anholt
2007-11-19[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt
2007-11-16[intel] Add 965 support to shared intel_blit.cEric Anholt
This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16[i915] Pass static region names in so debugging says more than "static region".Eric Anholt
2007-11-16[intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt
2007-11-16[intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt
2007-11-16[965] Add batchbuffer decode for several more packets.Eric Anholt
2007-11-16[intel] Fix typos in intel_chipset.h macros.Eric Anholt
2007-11-16[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt
2007-11-16[i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.Eric Anholt
2007-11-16[intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt
2007-11-16[intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt
This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
2007-11-16[intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt
They shouldn't be created, and this often helps catch stupid issues.
2007-11-16[intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt
This is required for 965 support, which has relocations in other places than just the batchbuffer.
2007-11-16[i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt
The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
2007-11-15fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger
this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
2007-11-12i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730Xiang, Haihao
2007-11-09[i915] Remove old frontbuffer rotation hack.Eric Anholt
This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately.
2007-11-09[intel] By default, output batchbuffer decode to stderr like other debug info.Eric Anholt
2007-11-09[intel] Initialize a depth buffer if the visual has depth 24 but no stencil.Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt
2007-11-09code clean-ups, reformattingBenno Schulenberg
2007-11-09recreate from changed gl_API.xmlRoland Scheidegger
2007-11-08fix Unichrome/Blender crash, bug 13142Benno Schulenberg
2007-11-06r200: Re-expose SetTexOffset functionality.Michel Dänzer
This seems to have been mismerged with the DRI interface changes.
2007-11-06r200: Fix SetTexOffset format for 16 bit pixmaps/textures.Michel Dänzer
Use symbolic array indices to clarify.
2007-11-05Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL.Oliver McFadden
2007-11-05r300: initial user clipping for TCL pathsDave Airlie
I've no idea if this code might break something or how it should interact with vertex shaders, it makes the clip demo work for me
2007-11-03fix typoBrian
2007-11-03r300: move more vap registers out of non tcl pathsDave Airlie
2007-11-03r300: fix misnumber registerDave Airlie
2007-11-03r300: fix texwrap border colorDave Airlie
2007-11-01nouveau: ppc, swap fragment programs on big endian systems.Dave Airlie
Thanks to the PS3 RSX project for figuring this out.
2007-11-01i915: make i915 use the cached mappings for batch/buffer objects.Dave Airlie
This should restore gears speed on 9xx hardware
2007-10-31Merge branch 'master' of git+ssh://joukj@git.freedesktop.org/git/mesa/mesaJouk
2007-10-30Alias glStencilOpSeparateATI with glStencilOpSeparate.Brian
2007-10-30Finish up ATI_separate_stencilBrian
Add entrypoints to glapi XML file and regenerate files. Implement glStencilOpSeparateATI(). Consolidate some code in stencil.c
2007-10-30More vblank cleanups.Michel Dänzer
* Fix crash at context creation in most drivers supporting vblank. * Don't pass vblank sequence or flags to functions that get passed the drawable private already. * Attempt to initialize vblank related drawable private fields just once per drawable. May need more work in some drivers.
2007-10-29[i915] Include header to pick up intel_ttm_bo_create_from_handle() proto.Eric Anholt
2007-10-29Merge branch 'origin'Eric Anholt
2007-10-29Refactor and fix core vblank supportJesse Barnes
Consolidate support for synchronizing to and retrieving vblank counters. Also fix the core vblank code to return monotonic MSC counters, which are required by some GLX extensions. Adding support for multiple pipes to a low level driver is fairly easy, the Intel 965 driver provides simple example code (see intel_buffers.c:intelWindowMoved()). The new code bumps the media stream counter extension version to 2 and adds a new getDrawableMSC callback. This callback takes a drawablePrivate pointer, which is used to calculate the MSC value seen by clients based on the actual vblank counter(s) returned from the kernel. The new drawable private fields are as follows: - vblSeq - used for tracking vblank counts for buffer swapping - vblFlags - flags (e.g. current pipe), updated by low level driver - msc_base - MSC counter from the last time the current pipe changed - vblank_base - kernel DRM vblank counter from the last time the pipe changed Using the above variables, the core vblank code (in vblank.c) can calculate a monotonic MSC value. The low level DRI drivers are responsible for updating the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags) along with msc_base and vblank_base whenever the pipe associated with a given drawable changes (again, see intelWindowMoved for an example of this). Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to driDrawableGetMSC32 and add code for pipe switching as outlined above to fully support the new scheme.
2007-10-26Merge branch '965-glsl'Zou Nan hai
Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
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