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2009-11-09r600: rework DB render setupAlex Deucher
- consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z
2009-11-09r600: don't emit htile regsAlex Deucher
These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm.
2009-11-09r600: add missing ZPASS setup bits for r7xx+Alex Deucher
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix issues with antialiased lines in GLSL.
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
2009-11-06i965: Collect GLSL src/dst regs up in generic code.Eric Anholt
This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
2009-11-06intel: better front color buffer test in intelClear()Brian Paul
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
This keeps the individual state files from having to export their structures for brw_state_cache initialization.
2009-11-06intel: Finish removing the fallback code for bug #16697.Eric Anholt
I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
2009-11-06intel: Don't validate in a texture image used as a render target.Eric Anholt
Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation.
2009-11-06intel: Clean up some extra struct indirection in finalize.Eric Anholt
2009-11-06intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt
2009-11-06intel: Remove duplicated arguments from intel_miptree_match_image().Eric Anholt
2009-11-06i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt
2009-11-06intel: Remove obsolete comment about GEM in the spans code.Eric Anholt
2009-11-06intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt
This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
2009-11-06Make a convenient int for what chipset generation we're on.Eric Anholt
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks.
2009-11-06Merge branch 'mesa_7_6_branch'Ian Romanick
This should fix the memory leaks in the assembly parser without the regressions. The conflicts in program_lexer.l were related to changes in returning strings between the branches (always return IDENTIFIER vs. returing either IDENTIFIER or USED_IDENTIFIER). The conflicts in program_parse.y were related to two changes in master One change prints a variable name in an error message. The other change adds outputVarSize to the OUTPUT_statement rule. The cause the position of the IDENTIFIER to change from $2 to $3. Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_lexer.l src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.y
2009-11-06intel: call intel_check_front_buffer_rendering() in intelClear()Brian Paul
fixes bug 24953.
2009-11-05xmesa: pass pixmap to clip_for_xgetimage()Brian Paul
The code was assuming ctx->DrawBuffer == ctx->ReadBuffer. Passing the pixmap is simpler and better. Fixes a potential segfault.
2009-11-04Merge branch 'mesa_7_6_branch'Brian Paul
Conflicts: src/mesa/drivers/windows/gdi/mesa.def
2009-11-04r600: rework draw functionsAlex Deucher
Seems INDX_OFFSET doesn't work properly on some cards, so change back to immediate mode indices. Seems to only affect DRI1. Needs more investigation. Rework and clean up the draw functions. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-11-04r600: fix count prediction for IB caseAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-11-04Fix YTILE spantmp functionsAlan Hourihane
2009-11-04Fix YTILE spantmp functionsAlan Hourihane
2009-11-04glslcompiler: Fix Mac OS build.Vinson Lee
Signed-off-by: Brian Paul <brianp@vmware.com>
2009-11-03windows: remove old entrypoints from mesa.def fileKarl Schultz
Signed-off-by: Brian Paul <brianp@vmware.com>
2009-11-03Merge branch 'mesa_7_6_branch'Brian Paul
2009-11-03intel: avoid unnecessary front buffer flushing/updatingBrian Paul
Before, if we just called glXMakeCurrent() and didn't render anything we'd still trigger a flushFrontBuffer() call. Now only set the intel->front_buffer_dirty field at state validation time just before we draw something. NOTE: additional calls to intel_check_front_buffer_rendering() might be needed if I missed some rendering paths.
2009-11-02mesa: use _mesa_get_current_tex_object()Brian Paul
2009-11-02r600: implement LOG op in compilerPierre Ossman
2009-11-02r600: implement EXP op in compilerPierre Ossman
2009-10-31radeon: add missing includeDave Airlie
2009-10-31radeon: use _mesa_get_current_tex_unitDave Airlie
2009-10-30intel: Use GTT mapping when available for swrast.Eric Anholt
This improves piglit quick.tests runtime from 19:33 minutes to 6:06 on my GM45. It should also hide most of the A17 swizzling issues, though they'll still exist when swapping occurs (which is the kernel's problem either way).
2009-10-30intel: Fix up z24_x8 depth spans since the texformat merge.Eric Anholt
2009-10-30i965: Add an index assert on get_fp_inst array like other compiler arrays.Eric Anholt
2009-10-30i965: Fix BRW_WM_MAX_INSN to reflect current limits.Eric Anholt
Part of fixing bug #24355.
2009-10-30intel: Set the texture format in the TFP path.Eric Anholt
This fixes a regression in piglit's tfp test as of 11caea687e3f10ae12d33e44edf84635f73047dd. Additionally, set the texture format for the RGB textures to MESA_FORMAT_XRGB8888 and support it in the hw paths so that hopefully sw fallbacks involving TFP get better alpha behavior. The radeon drivers appear to need the same fix. Bug #24803
2009-10-30r600: remove duplicate lineAlex Deucher
2009-10-30r600: fill in some missing tex formatsAlex Deucher
This improves shadowtex since the component ordering is at least correct now, but I'm not sure how to deal with texturing from a depth surface yet due to differences in depth and color tile layouts. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>