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2009-06-23Fix crash when debug output is enabled and sarea is notset in r200ClearPauli Nieminen
2009-06-22i965: Fix warnings in intel_pixel_read.c.Eric Anholt
2009-06-22intel: Fix glReadPixels regression since changing context init order.Michel Dänzer
Fixes regression in dd26899ca39111e0866afed9df94bfb1618dd363 that also affected some PBO operations.
2009-06-19intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
2009-06-19intel: Update Mesa state before span setup in glReadPixels.Eric Anholt
We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue.
2009-06-19intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt
2009-06-19intel: Don't map regions with drm_intel_gem_bo_map_gtt() unless they're tiled.Eric Anholt
This fixes a regression in region read performance that came in with the texture tiling changes. Ideally we'd have an access flag coming in so we could also use bo_map_gtt for writing, like we do for buffer objects. Bug #22190
2009-06-19intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt
Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least.
2009-06-19intel: Fix glClear behavior versus display lists.Eric Anholt
The CALL_DrawArrays was leaking the clear's primitives into the display list with GL_COMPILE_AND_EXECUTE. Use _mesa_DrawArrays instead, which doesn't appear to leak. Fixes piglit dlist-clear test.
2009-06-19intel: Do not access pbo's buffer directly when attaching.Chia-I Wu
pbo might be system buffer based or attached to another region. Call intel_bufferobj_buffer to make sure pbo has a buffer of its own. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-19intel: Data are copied in the wrong direction when breaking COW tie.Chia-I Wu
Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-19intel: Fix migration from sys_buffer in intel_bufferobj_buffer.Chia-I Wu
intel_bufferobj_subdata is called to migrate data from sys_buffer, and it expects only one of buffer or sys_buffer is non-NULL. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-20radeon: make cubemap mipmap generation workRoland Scheidegger
need to pass target parameter to radeon_teximage/radeon_subteximage functions otherwise mipmap generation for cube maps can't work (assert/segfault in _mesa_generate_mipmap)
2009-06-12i965: interpolate colors with perspective correction by defaultBrian Paul
...rather than with linear interpolation. Modern hardware should use perspective-corrected interpolation for colors (as for texcoords). glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get linear interpolation if mode = GL_FASTEST.
2009-06-12r300: add support for EXT_texture_sRGBMaciej Cencora
Tested with glean/texture_srgb and wine/d3d9 tests on RV535
2009-06-12Merge master and fix conflictsAlex Deucher
2009-06-12Merge branch 'mesa_7_5_branch'Jakob Bornecrantz
2009-06-12radeon: fix size of mipmap texture arrayDave Airlie
2009-06-12radeon/r200/r300: fix max texture levels assertDave Airlie
use the actual value set in the context
2009-06-12Merge remote branch 'main/radeon-rewrite'Dave Airlie
2009-06-11Add RV740 supportAlex Deucher
2009-06-11r300: fix VAP setupMaciej Cencora
If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
2009-06-11r300: fix for SW TCL pathMaciej Cencora
We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
2009-06-11r300: don't send unused attributes for SW TCL pathMaciej Cencora
2009-06-11r300: send only RS_IP_* regs that we are going to useMaciej Cencora
2009-06-11r300: fix RS setup when no colors and textures are sent to FPMaciej Cencora
RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
2009-06-11r300: r500 fragment program fixesMaciej Cencora
- when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory
2009-06-11radeon: increase max bo countMaciej Cencora
2009-06-11r300: fix a GPU lock upMaciej Cencora
Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK.
2009-06-11r300: fix vertex program bugMaciej Cencora
If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
2009-06-11r300: move some code for easier debuggingMaciej Cencora
2009-06-11r300: print vertex program when debugging is enabledMaciej Cencora
2009-06-11r300: fix output register allocation for vertex shadersMaciej Cencora
If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
2009-06-11r300: hw doesn't support saturation for tex instructionsMaciej Cencora
2009-06-11mesa: add default function for ctx->Driver.CheckQuery() hookBrian Paul
2009-06-11r300: fix indexed primitive rendering when using memory managerJerome Glisse
2009-06-11Properly set aos_countAlex Deucher
This is used by radeonReleaseArrays to free AOS.
2009-06-11intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer
Fixes glean depthStencil test.
2009-06-10move radeon_set_screen_flags() up so CHIP_FAMILY is set before using itAlex Deucher
fixes last commit.
2009-06-10Use correct scratch reg offset for r6xx/r7xxAlex Deucher
2009-06-10r300: make sure indexed rendering doesn't try to use more than the num of ↵Jerome Glisse
vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer.
2009-06-09Pull in additional state setup from the DDXAlex Deucher
2009-06-09i915: Add an option for testing the effect of early Z in classic mode.Eric Anholt
The early Z stuff is supposed to be unsafe without some more work in the enable/disable path (in particular, how do we want to get it disabled on the way out to the X Server?), but at the moment is 6% in OA.
2009-06-09intel: Remove an unneeded hunk that slipped in with texture tiling.Eric Anholt
intel_miptree_pitch_align does this later on.
2009-06-09intel: Base tri clearing depth on Y tiling, not IS_I965().Eric Anholt
Y tiling is why the 965 check was there, but I wanted to experiment with Y on pre-965 as well.
2009-06-09intel: Fix intel_region_unmap to do unmap, not map.Eric Anholt
Thanks to Shuang He for catching this.
2009-06-09i965: added intelFlush() call in intel_get_tex_image()Brian Paul
Fixes the render-to-texture test in progs/tests/getteximage.c
2009-06-09intel: use GLboolean, not int, for compressed parameterBrian Paul
2009-06-09intel: make a bunch of glTexImage-related functions staticBrian Paul
2009-06-09intel: whitespace clean-upsBrian Paul