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2008-03-19[i915] fix fragment.positionZou Nan hai
2008-03-18[i915] Bug #13634: Fix bugs in 945 cube mipmap layout.Eric Anholt
The most egregious, and the one the bug report and failure in the cubemap demo were about was introduced with intel_mipmap_pitch_align(), where a "* 2" for the pitch calculation was lost. The base size < 32 case also failed to align, which may have caused problems with render to texture. Another bug would have broken 2x2/1x1 base mipmap levels by placing the data where the hardware wouldn't look for it. Other bugs remain with the layout of the small mipmap faces (hardware looks for them in X,Y,Z,-X,-Y,-Z order along the bottom row, but we lay them out X,-X,Y,-Y,Z,-Z).
2008-03-18[i915] Add comments about how cube texture layout works.Eric Anholt
2008-03-18[i915] Move miptree layout code into separate functions per target.Eric Anholt
Also clean up some other miscellaneous formatting nits while I'm at it.
2008-03-18[intel] Clarify miptree layout by using byte offsets to images.Eric Anholt
2008-03-18[945] Remove conditional in 945 3D mipmap layout checking for cube layout.Eric Anholt
2008-03-18Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and ↵Zou Nan hai
GL_LINE_STRIP" There is no information in GS to determinate when to reset line stipple count, still fallback to software This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
2008-03-18[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIPZou Nan hai
2008-03-18r300: add new rs690 pci idDave Airlie
2008-03-17[965] Fix fp temp reg release code to not usually release all temps.Andrzej Trznadel
Also, use wrapped ffs() instead of native.
2008-03-17r300: Simplify r300VAPInputRoute1.Markus Amsler
2008-03-17r300: Simplify r300VAPInputRoute0, check for valid input.Markus Amsler
2008-03-17[i965] round pointsize to nearest int according to specZou Nan hai
2008-03-17intel: fix the error in commit 7ed1fd5d8438e55fe24091844cdfccb0881306bcXiang, Haihao
2008-03-17intel: It is needed to allocating texture memory to accommodateXiang, Haihao
a texture when calling TexImage with pixels set to NULL pointer.
2008-03-17intel: Remove an assertion from intel_miptree_create. TexImageXiang, Haihao
call with zero width/height/depth matches GL spec.
2008-03-17 [i965] fix wpos height 1 pixel higherZou Nan hai
2008-03-14intel: fix abort issue with shadowtex demo when useXiang, Haihao
DEPTH_STENCIL texture. (bug#14952).
2008-03-13 [i965] multiple rendering target supportZou Nan hai
2008-03-09DRI2: Make setTexBuffer take a __DRIdrawable instead of a BO handle.Kristian Høgsberg
This fixes a problem where texturing from the same Pixmap more than once per batchbuffer would hang the DRI driver. We just use the region associated with the front left renderbuffer of the __DRIdrawable for texturing, which avoids creating different regions for the same BO. This change also make GLX_EXT_texture_from_pixmap work for direct rendering, since tracking the __DRIdrawable -> BO handle now uses the standard DRI2 event buffer. Of course, DRI2 direct rendering doesn't exist yet. Finally, this commit bumps the DRI interface version again, accounting for the change in the DRI_TEX_BUFFER extension and the change in commit 0bba0e5be7a4a7275dad1edc34bdcc134ea1f424 to pass in the event buffer head index on drawable creation.
2008-03-09DRI2: Drop DriverAPI.UpdateBuffer.Kristian Høgsberg
__dri2ParseEvents() would determine the kind of event, but then call UpdateBuffer() in either case, and UpdateBuffer() would then have to figure that out again to dispatch to HandleBufferAttach() or HandleDrawableConfig(). Pretty pointless.
2008-03-09DRI2: Pass the context instead of the screen to __dri2ParseEvents().Kristian Høgsberg
Makes a lot more sense, since the screen is always implicit in the DRI drawable, but it may not be possible to track down a context from just a drawable.
2008-03-09DRI2: Add event buffer head as an argument to driCreateNewDrawable().Kristian Høgsberg
The DRI driver needs to know where in the buffer to start reading.
2008-03-07[intel] Only enable GL_EXT_texture_sRGB on i965.Kristian Høgsberg
Fixes #14799.
2008-03-07 [i965] fix fd.o bug #11471 and #11478Zou Nan hai
1. Follow EXT_texture_rectangle with YCbCr texture 2. swap UV component for MESA_FORMAT_YCBCR
2008-03-07i965: use RGB565 to render a bitmap if Depth is 16Xiang, Haihao
2008-03-06i965: Fix double free issue to pass glean/maskedClear testXiang, Haihao
2008-03-06i965:fix segfault issue when clearing the window whichXiang, Haihao
is created with mode GLUT_SINGLE|GLUT_RGB|GLUT_DEPTH. This issue is introduced by 20b8bff49cba3e8246e29004c5ff38f231d589ff
2008-03-05[intel] Add a driconf option to cache freed buffer objects for reuse.Eric Anholt
This is defaulted off as it has potentially large memory costs for a modest performance gain. Ideally we will improve DRM performance to the point where this optimization is not worth the memory cost in any case, or find some middle ground in caching only limited numbers of certain buffers. For now, this provides a modest 4% improvement in openarena on GM965 and 10% in openarena on GM945.
2008-03-04r300: replace some hard coded mask by define in stencil areaChristoph Brill
2008-03-04r300: Fix some issues with masks in stencil buffer areaChristoph Brill
2008-03-03[dri2] Add tail pointer to reemitDrawableInfo callback.Kristian Høgsberg
When the DRI doesn't parse the event buffer for a while, the X server may overwrite data that the driver didn't get a chance to look at. The reemitDrawableInfo callback requests that the X server reemit all info for the specified drawable. To make use of this, the drive needs to know the new tail pointer so it know where to start reading from.
2008-03-03[dri2] Optimize event parsing to skip obsolete events.Kristian Høgsberg
This also fixes the problem where the X server does multiple resizes before the DRI driver gets the events. The obsolete buffer attach events then reference already destroyed buffer objects.
2008-03-03[intel] Silence unused variable warning when compiling for i965.Kristian Høgsberg
2008-03-02nouveau: compilation fixesPatrice Mandin
2008-03-02r300: Corrected a bug with the SUB instruction.Oliver McFadden
2008-03-02r300: Corrected a bug with the MAD instruction.Oliver McFadden
The PVS_VECTOR_OPCODE macro should be modified to support macro instructions, too.
2008-03-01r300: Added the PVS_SRC_OPERAND documentation from AMD.Oliver McFadden
2008-03-01r300: Added the PVS_OP_DST_OPERAND documentation from AMD.Oliver McFadden
2008-03-01r300: Added a TODO comment for registers missing from AMD's documentation.Oliver McFadden
2008-03-01r300: Moved the vertex program shift/mask defines into the appropriate file.Oliver McFadden
2008-03-01r300: Indented the vertex program code with longer lines.Oliver McFadden
2008-03-01r300: Moved the PREFER_DP4 define near the position invariant function.Oliver McFadden
2008-03-01r300: Added a TODO comment for the MAD opcodes.Oliver McFadden
2008-03-01r300: Use the VE_ADD hardware opcode for the SUB opcode.Oliver McFadden
2008-03-01r300: Use the VE_MULTIPLY hardware opcode for the MUL opcode.Oliver McFadden
2008-03-01r300: Cleaned up the XPD opcode temporary register usage.Oliver McFadden
2008-03-01r300: Cleaned up extra white space.Oliver McFadden
2008-03-01r300: Prefer to use the VE_ADD for simple MOV style opcodes.Oliver McFadden
The VE_MULTIPLY_ADD has further restrictions on reading temporary memory which may complicate things. See AMD's documentation.
2008-03-01r300: Removed the (undocumented) MAD_2 opcode.Oliver McFadden
This opcode is likely a mistake from reverse engineering. MAD_2 isn't included in AMD's documentation, and my testing reviles there is no problem using the documented MAD opcode.
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